DSPIC30F1010-20E/MM Microchip Technology, DSPIC30F1010-20E/MM Datasheet - Page 166
DSPIC30F1010-20E/MM
Manufacturer Part Number
DSPIC30F1010-20E/MM
Description
6KB, Flash, 256bytes-RAM, 30MIPS, 21I/O, 16-bit Family,nanoWatt 28 QFN-S 6x6mm T
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.AC164335.pdf
(286 pages)
2.DM300023.pdf
(22 pages)
3.DM300023.pdf
(18 pages)
4.DSPIC30F2011-20ISO.pdf
(66 pages)
5.DSPIC30F2011-20IP.pdf
(26 pages)
6.DSPIC30F1010-30ISO.pdf
(26 pages)
7.DSPIC30F1010-30ISO.pdf
(50 pages)
Specifications of DSPIC30F1010-20E/MM
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
6KB (2K x 24)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM300023 - KIT DEMO DSPICDEM SMPS BUCK
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F1010-20E/MM
Manufacturer:
Microchip Technology
Quantity:
135
Part Number:
DSPIC30F1010-20E/MM
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- AC164335 PDF datasheet
- DM300023 PDF datasheet #2
- DM300023 PDF datasheet #3
- DSPIC30F2011-20ISO PDF datasheet #4
- DSPIC30F2011-20IP PDF datasheet #5
- DSPIC30F1010-30ISO PDF datasheet #6
- DSPIC30F1010-30ISO PDF datasheet #7
- Current page: 166 of 286
- Download datasheet (5Mb)
dsPIC30F1010/202X
REGISTER 15-1:
DS70178C-page 164
bit 15
bit 7
Legend: U = Unimplemented bit, read as ‘0’
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9-8
bit 7
bit 6
bit 5
bit 4
bit 3
R/W-0 HC
UARTEN
R/W-0
WAKE
UARTEN: UART1 Enable bit
1 = UART1 enabled; all UART1 pins are controlled by UART1 as defined by UEN<1:0>
0 = UART1 disabled; all UART1 pins are controlled by PORT latches; UART1 power consumption minimal
Unimplemented: Read as ‘0’
USIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
IREN: IrDA Encoder and Decoder Enable bit
1 = IrDA encoder and decoder enabled
0 = IrDA encoder and decoder disabled
Unimplemented: Read as ‘0’
ALTIO: UART Alternate I/O Selection bit
1 = UART communicates using U1ATX and U1ARX I/O pins
0 = UART communicates using U1TX and U1RX I/O pins.
Unimplemented: Read as ‘0’
WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit
1 = UART1 will continue to sample the U1RX pin; interrupt generated on falling edge, bit cleared in
0 = No wake-up enabled
LPBACK: UART1 Loopback Mode Select bit
1 = Enable Loopback mode
0 = Loopback mode is disabled
ABAUD: Auto-Baud Enable bit
1 = Enable baud rate measurement on the next character – requires reception of a Sync field (55h);
0 = Baud rate measurement disabled or completed
RXINV: Receive Polarity Inversion bit
1 = U1RX Idle state is ‘0’
0 = U1RX Idle state is ‘1’
BRGH: High Baud Rate Enable bit
1 = BRG generates 4 clocks per bit period (4x Baud Clock, High-Speed mode)
0 = BRG generates 16 clocks per bit period (16x Baud Clock, Standard mode)
LPBACK
Note:
R/W-0
hardware on following rising edge
cleared in hardware upon completion
U-0
—
U1MODE: UART1 MODE REGISTER
This feature is only available for the 16x BRG mode (BRGH = 0).
W = Writable bit
‘1’ = Bit is set
R/W-0 HC
ABAUD
USIDL
R/W-0
RXINV
R/W-0
R/W-0
IREN
Preliminary
HC = Hardware Cleared
‘0’ = Bit is cleared
R/W-0
BRGH
U-0
—
PDSEL1
R/W-0
ALTIO
R/W-0
© 2006 Microchip Technology Inc.
HS = Hardware Select
x = Bit is unknown
PDSEL0
R/W-0
U-0
—
STSEL
R/W-0
U-0
—
bit 8
bit 0
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