LP8900TLX-3333 National Semiconductor, LP8900TLX-3333 Datasheet - Page 9

• Manufacturer Part Number: LP8900TLX-3333
• Description: REG ULN, DUAL, 200MA, 6-MICROSMD
• Manufacturer: National Semiconductor

Specifications of LP8900TLX-3333

• Primary Input Voltage: 3.8V
• Output Voltage: 3.6V
• Dropout Voltage Vdo: 110mV
• No. Of Pins: 6
• Output Current: 200mA
• Operating Temperature Range: -40°C To +125°C
• Svhc: No SVHC (15-Dec-2010)
• Operating: RoHS Compliant
• Output Voltage Fixed: 3.6V
• Voltage Regulator Case Style: Micro SMD
• Rohs Compliant: Yes

Application Information
EXTERNAL CAPACITORS
In common with most regulators, the LP8900 requires exter-
nal capacitors for regulator stability. The LP8900 is specifi-
cally designed for portable applications requiring minimum
board space and smallest components. These capacitors
must be correctly selected for good performance.
INPUT CAPACITOR
An input capacitor is required for stability. It is recommended
that a 1.0µF capacitor be connected between the LP8900 in-
put pin and ground (this capacitance value may be increased
to 10µF).
This capacitor must be located a distance of not more than
1cm from the input pin and returned to a clean analogue
ground. Any good quality ceramic, tantalum, or film capacitor
may be used at the input.
Important: Tantalum capacitors can suffer catastrophic fail-
ures due to surge current when connected to a low-
impedance source of power (like a battery or a very large
capacitor). If a tantalum capacitor is used at the input, it must
be guaranteed by the manufacturer to have a surge current
rating sufficient for the application.
There are no requirements for the ESR (Equivalent Series
Resistance) on the input capacitor, but tolerance, tempera-
ture, and voltage coefficients must be considered when se-
lecting the capacitor to ensure the capacitance will remain
1.0µF over the entire operating temperature range.
OUTPUT CAPACITOR
Correct selection of the output capacitor is critical to ensure
stable operation in the intended application.
The output capacitor must meet all the requirements specified
in the recommended capacitor table over all conditions in the
application. These conditions include DC bias, frequency and
temperature. Unstable operation will result if the capacitance
drops below the minimum specified value.
The LP8900 is designed specifically to work with very small
ceramic output capacitors. A 1.0µF ceramic capacitor (dielec-
tric type X7R or X5R) with an ESR between 5mΩ to 500mΩ,
is suitable in the LP8900 application circuit.
Other ceramic types such as Y5V and Z5U are less suitable
owing to their inferior temperature characteristics. (See sec-
tion on Capacitor Characteristics).
It is also recommended that the output capacitor is placed
within 1cm of the output pin and returned to a clean, low
impedance, ground connection.
It is possible to use tantalum or film capacitors at the device
output, V
size and cost (see the section Capacitor Characteristics).
NO-LOAD STABILITY
The LP8900 will remain stable and in regulation with no ex-
ternal load. This is an important consideration in some cir-
cuits, for example CMOS RAM keep-alive applications.
CAPACITOR CHARACTERISTICS
The LP8900 is designed to work with ceramic capacitors on
the input and outputs to take advantage of the benefits they
offer. For capacitance values around 1.0µF, ceramic capaci-
tors give the circuit designer the best design options in terms
of low cost and minimal area.
For both input and output capacitors, careful interpretation of
the capacitor specification is required to ensure correct device
OUT
, but these are not as attractive for reasons of
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operation. The capacitor value can change greatly dependant
on the conditions of operation and capacitor type.
In particular, to ensure stability, the output capacitor selection
should take account of all the capacitor parameters, to ensure
that the specification is met within the application. Capaci-
tance value can vary with DC bias conditions as well as
temperature and frequency of operation. Capacitor values will
also show some decrease over time due to aging. The ca-
pacitor parameters are also dependant on the particular case
size with smaller sizes giving poorer performance figures in
general.
As an example Figure 1 shows a typical graph showing a
comparison of capacitor case sizes in a Capacitance vs. DC
Bias plot. As shown in the graph, as a result of the DC Bias
condition, the capacitance value may drop below the mini-
mum capacitance value given in the recommended capacitor
table. Note that the graph shows the capacitance out of spec
for the 0402 case size capacitor at higher bias voltages. It is
therefore recommended that the capacitor manufacturers'
specifications for the nominal value capacitor are consulted
for all conditions as some capacitor sizes (e.g. 0402) may not
be suitable in the actual application. Ceramic capacitors have
the lowest ESR values, thus making them best for eliminating
high frequency noise. The ESR of a typical 4.7µF ceramic
capacitor is in the range of 20mΩ to 40mΩ, which easily
meets the ESR requirement for stability for the LP8900. The
temperature performance of ceramic capacitors varies by
type. Capacitor type X7R is specified with a tolerance of ±15%
over the temperature range -55°C to +125°C. The X5R has a
similar tolerance over the reduced temperature range of -55°
C to +85°C. Some large value ceramic capacitors (4.7µF) are
manufactured with Z5U or Y5V temperature characteristics,
which can result in the capacitance dropping by more than
50% as the temperature varies from 25°C to 85°C. Therefore
X7R or X5R types are recommended in applications where
the temperature will change significantly above or below 25°
C.
Tantalum capacitors are less desirable than ceramic for use
as output capacitors because they are more expensive when
comparing equivalent capacitance and voltage ratings in the
1µF to 4.7µF range. Another important consideration is that
tantalum capacitors have higher ESR values than equivalent
size ceramics. This means that while it may be possible to find
a tantalum capacitor with an ESR value within the stable
FIGURE 1. Effect of DC bias on Capacitance Value.
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