A8498SLJ-T Allegro Microsystems Inc, A8498SLJ-T Datasheet - Page 5

• Manufacturer Part Number: A8498SLJ-T
• Description: IC, STEP-DOWN VOLTAGE REGULATOR, SOIC-8
• Manufacturer: Allegro Microsystems Inc
• Type: Step-Down (Buck)r

Specifications of A8498SLJ-T

• Primary Input Voltage: 50V
• No. Of Outputs: 1
• Output Voltage: 24V
• Output Current: 3A
• No. Of Pins: 8
• Operating Temperature Range: -20°C To +85°C
• Leaded Process Compatible: Yes
• Internal Switch(s): Yes
• Synchronous Rectifier: No
• Number Of Outputs: 1
• Voltage - Output: 0.8 ~ 24 V
• Current - Output: 3A
• Voltage - Input: 8 ~ 50 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width) Exposed Pad, 8-eSOIC. 8-HSOIC
• Voltage Regulator Case Style: SOIC
• Svhc: No SVHC
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -
• Frequency - Switching: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

A8498
The A8498 is a fixed off-time, current-mode–controlled buck
switching regulator. The regulator requires an external clamping
diode, inductor, and filter capacitor, and operates in both continu-
ous and discontinuous modes. An internal blanking circuit is used
to filter out transients resulting from the reverse recovery of the
external clamp diode. Typical blanking time is 200 ns.
The value of a resistor between the TSET pin and ground deter-
mines the fixed off-time (see graph in the t
V
the combination of the value of the external resistor divider and
the internal 0.8 V ±2% reference. The voltage can be calculated
with the following formula:
Light Load Regulation. To maintain voltage regulation during
light load conditions, the switching regulator enters a cycle-skip-
ping mode. As the output current decreases, there remains some
energy that is stored during the power switch minimum on-time.
In order to prevent the output voltage from rising, the regulator
skips cycles once it reaches the minimum on-time, effectively
making the off-time larger.
Soft Start. An internal ramp generator and counter allow the out-
put to slowly ramp up. This limits the maximum demand on the
external power supply by controlling the inrush current required
to charge the external capacitor and any dc load at startup.
Internally, the ramp is set to 10 ms nominal rise time. During soft
start, current limit is 3.5 A minimum.
The following conditions are required to trigger a soft start:
• V
• ENB pin input falling edge
• Reset of a TSD (thermal shut down) event
V
V
bias current during normal operating conditions. During startup
the circuitry is run off of the VIN supply. VBIAS should be con-
nected to VOUT when the V
5 V. If the output voltage is less than 3.3 V, then the A8498 can
operate with an internal supply and pay a penalty in efficiency,
as the bias current will come from the high voltage supply, VIN.
VBIAS can also be supplied with an external voltage source. No
power-up sequencing is required for normal operation.
ON/OFF Control. The ENB pin is externally pulled to ground
OUT
BIAS
OUT
IN
, is connected to the VBIAS input to supply the operating
. The output voltage is adjustable from 0.8 to 24 V, based on
. To improve overall system efficiency, the regulator output,
> 6 V
V
OUT
= V
FB
OUT
× (1 + R1/R2)
target level is between 3.3 and
Wide Input Voltage 3.0 A Step Down Regulator
OFF
section).
Functional Description
(1)
to enable the device and begin the soft start sequence. When the
ENB is open circuited, the switcher is disabled and the output
decays to 0 V.
Protection. The buck switch will be disabled under one or more
of the following fault conditions:
• V
• ENB pin = open circuit
• TSD fault
When the device comes out of a TSD fault, it will go into a soft
start to limit inrush current.
t
determines the fixed off-time. The formula to calculate t
is:
where R
in the following graph:
t
time, t
where
OFF
ON
V
R
R
f
. From the volt-second balance of the inductor, the turn-on
L
DS(on)
IN
. The value of a resistor between the TSET pin and ground
is the voltage drop across the external Schottky diode,
is the winding resistance of the inductor, and
200
180
160
140
120
100
on
< 6 V
80
60
40
20
t
0
ON
TSET
, can be calculated approximately by the equation:
1
t
is the on-resistance of the switching MOSFET.
OFF
=
2
(kΩ) is the value of the resistor. Results are shown
V
3
=
IN
Off-Time Setting versus Resistor Value
4
R
– I
(V
TSET
5
OUT
OUT
6
V
BIAS
115 Northeast Cutoff, Box 15036
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 [phone]
www.allegromicro.com
+ V
⎛
⎜
⎝
7
1–0.03 V
t
R
OFF
= 5 V
10.2 × 10
DS(on)
f
8
+ I
(µs)
9
OUT
10
– I
BIAS
9
OUT
11 12 13 14 15
V
R
⎞
⎟
⎠
BIAS
L
) t
,
= 3.3 V
R
L
OFF
– V
OUT
OFF
16
(2)
(μs)
(3)
5