ZL6100EVAL1Z Intersil, ZL6100EVAL1Z Datasheet - Page 17

• Manufacturer Part Number: ZL6100EVAL1Z
• Description: EVAL BOARD USB ZL6100
• Manufacturer: Intersil

Specifications of ZL6100EVAL1Z

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DESIGN GOAL TRADE-OFFS
The design of the buck power stage requires several
compromises among size, efficiency, and cost. The inductor
core loss increases with frequency, so there is a trade-off
between a small output filter made possible by a higher
switching frequency and getting better power supply
efficiency. Size can be decreased by increasing the
switching frequency at the expense of efficiency. Cost can
be minimized by using through-hole inductors and
capacitors; however these components are physically large.
To start the design, select a switching frequency based on
Table 14. This frequency is a starting point and may be
adjusted as the design progresses.
INDUCTOR SELECTION
The output inductor selection process must include several
trade-offs. A high inductance value will result in a low ripple
current (I
produce a low output ripple voltage, but may also
compromise output transient load performance. Therefore, a
balance must be struck between output ripple and optimal
load transient performance. A good starting point is to select
the output inductor ripple equal to the expected load
transient step magnitude (I
Input voltage (V
Output voltage (V
Output current (I
Output voltage ripple
(V
Output load step (I
Output load step rate
Output deviation due to loadstep
Maximum PCB temp.
Desired efficiency
Other considerations
I
OPP
FREQUENCY RANGE
orip
200kHz to 400kHz
400kHz to 800kHz
800kHz to 1.4MHz
)
=
TABLE 14. CIRCUIT DESIGN CONSIDERATIONS
TABLE 13. POWER SUPPLY REQUIREMENTS
PARAMETER
I
opp
OSTEP
), which will reduce output capacitance and
IN
OUT
)
OUT
ostep
)
)
)
ostep
EFFICIENCY
17
Moderate
Highest
Lower
; see Equation 5):
3.0V to 14.0V
< 3% of V
0.6V to 5.0V
0A to ~25A
RANGE
+120°C
Various
< Io
-
-
-
OUT
CIRCUIT SIZE
Optimize for
1% of V
EXAMPLE
Smallest
small size
Smaller
50% of I
Larger
VALUE
10A/µs
± 50mV
+85°C
1.2V
85%
12V
20A
(EQ. 5)
OUT
o
ZL6100
Now the output inductance can be calculated using
Equation 6, where V
The average inductor current is equal to the maximum
output current. The peak inductor current (I
using Equation 7 where I
Select an inductor rated for the average DC current with a
peak current rating above the peak current computed .
In overcurrent or short-circuit conditions, the inductor may
have currents greater than 2x the normal maximum rated
output current. It is desirable to use an inductor that still
provides some inductance to protect the load and the
MOSFETs from damaging currents in this situation.
Once an inductor is selected, the DCR and core losses in
the inductor are calculated. Use the DCR specified in the
inductor manufacturer’s datasheet.
I
where I
the core loss of the selected inductor. Since this calculation
is specific to each inductor and manufacturer, refer to the
chosen inductor datasheet. Add the core loss and the ESR
loss and compare the total loss to the maximum power
dissipation recommendation in the inductor datasheet.
OUTPUT CAPACITOR SELECTION
Several trade-offs must also be considered when selecting
an output capacitor. Low ESR values are needed to have a
small output deviation during transient load steps (V
low output voltage ripple (V
low ESR, such as semi-stable (X5R and X7R) dielectric
ceramic capacitors, also have relatively low capacitance
values. Many designs can use a combination of high
capacitance devices and low ESR devices in parallel.
For high ripple currents, a low capacitance value can cause
a significant amount of output voltage ripple. Likewise, in
high transient load steps, a relatively large amount of
capacitance is needed to minimize the output voltage
deviation while the inductor current ramps up or down to the
new steady state output current value.
P
Lrms
I
I
L
Lrms
Lpk
LDCR
OUT
is given by
=
=
OUT
=
=
I
V
OUT
DCR
I
OUT
is the maximum output current. Next, calculate
OUT
+
f
×
×
2
sw
I
+
⎛
⎜ ⎜
⎝
opp
I
2
1
×
Lrms
INM
( )
−
I
I
opp
12
opp
2
is the maximum input voltage:
V
V
OUT
OUT
INM
orip
2
is the maximum output current.
). However, capacitors with
⎞
⎟ ⎟
⎠
Lpk
) is calculated
December 15, 2010
osag
FN6876.2
(EQ. 6)
(EQ. 7)
(EQ. 8)
(EQ. 9)
) and