ZL6100EVAL1Z Intersil, ZL6100EVAL1Z Datasheet - Page 14

• Manufacturer Part Number: ZL6100EVAL1Z
• Description: EVAL BOARD USB ZL6100
• Manufacturer: Intersil

Specifications of ZL6100EVAL1Z

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Soft-start Delay and Ramp Times
It may be necessary to set a delay from when an enable
signal is received until the output voltage starts to ramp to its
target value. In addition, the designer may wish to precisely
set the time required for V
the delay period has expired. These features may be used
as part of an overall inrush current management strategy or
to precisely control how fast a load IC is turned on. The
ZL6100 gives the system designer several options for
precisely and independently controlling both the delay and
ramp time periods.
The soft-start delay period begins when the EN pin is
asserted and ends when the delay time expires. The
soft-start delay period is set using the DLY (0, 1) pins.
Precise ramp delay timing reduces the delay time variations
but is only available when the appropriate bit in the
MISC_CONFIG register has been set. Please refer to
Application Note AN2033 for details.
The soft-start ramp timer enables a precisely controlled ramp
to the nominal V
has expired. The ramp-up is guaranteed monotonic and its
slope may be precisely set using the SS pin.
The soft start delay and ramp times can be set to standard
values according to Tables 7 and 8 respectively.
Note: When the device is set to 0ms or 1ms delay, it will begin
its ramp up after the internal circuitry has initialized (~2ms).
DLY1
STEP
1
2
3
4
5
TABLE 7. SOFT-START DELAY SETTINGS
Power Applied
Internal Memory Check
Multi-mode Pin Check
Device Ready
Pre-ramp Delay
OPEN
HIGH
LOW
OUT
STEP NAME
value that begins once the delay period
OUT
LOW
(ms)
50
0
5
14
to ramp to its target value after
DLY0
OPEN
(ms)
100
10
1
Input voltage is applied to the ZL6100’s VDD pin Depends on input supply ramp time
The device will check for values stored in its
internal memory. This step is also performed after
a Restore command.
The device loads values configured by the multi-
mode pins.
The device is ready to accept an enable signal.
The device requires approximately 2ms following
an enable signal and prior to ramping its output.
Additional pre-ramp delay may be configured
using the Delay pins.
TABLE 6. ZL6100 START-UP SEQUENCE
HIGH
(ms)
200
20
2
DESCRIPTION
ZL6100
Note: When the device is set to 0ms ramp, it will attempt to
ramp as fast as the external load capacitance and loop
settings will allow. It is generally recommended to set the
soft-start ramp to a value greater than 500µs to prevent
inadvertent fault conditions due to excessive inrush current.
If the desired soft start delay and ramp times are not one of
the values listed in Tables 7 and 8, the times can be set to a
custom value by connecting a resistor from the DLY0 or SS
pin to SGND using the appropriate resistor value from
Table 9. The value of this resistor is measured upon start-up
or Restore and will not change if the resistor is varied after
power has been applied to the ZL6100. See Figure 12 for
typical connections using resistors.
DLY OR SS
(ms)
100
10
20
30
40
50
60
70
80
90
0
TABLE 9. DLY AND SS RESISTOR SETTINGS
TABLE 8. SOFT-START RAMP SETTINGS
OPEN
HIGH
LOW
SS
R
DLY
Approx 5ms to 10ms (device will ignore an
enable signal or PMBus traffic during this period)
-
Approximately 2ms
(kΩ)
12.1
13.3
14.7
16.2
17.8
19.6
21.5
23.7
26.1
OR R
10
11
SS
DLY OR SS
TIME DURATION
(ms)
110
120
130
140
150
160
170
180
190
200
RAMP TIME
(ms)
10
0
5
R
December 15, 2010
DLY
(kΩ)
28.7
31.6
34.8
38.3
42.2
46.4
51.1
56.2
61.9
68.1
OR R
FN6876.2
SS