ISL9305IRTBCNLZ-T Intersil, ISL9305IRTBCNLZ-T Datasheet - Page 7
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ISL9305IRTBCNLZ-T
Manufacturer Part Number
ISL9305IRTBCNLZ-T
Description
IC PMIC 800MA 3MHZ 16TQFN
Manufacturer
Intersil
Datasheet
1.ISL9305IRTAANLZ-T.pdf
(17 pages)
Specifications of ISL9305IRTBCNLZ-T
Topology
Step-Down (Buck) (2), Linear (LDO) (2)
Function
Any Function
Number Of Outputs
4
Frequency - Switching
3MHz
Voltage/current - Output 1
0.8 V ~ 5.5 V, 800mA
Voltage/current - Output 2
0.8 V ~ 5.5 V, 800mA
Voltage/current - Output 3
0.9 V ~ 3.3 V, 350mA
W/led Driver
No
W/supervisor
No
W/sequencer
No
Voltage - Supply
1.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
*
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Theory of Operation
DCD1 and DCD2 Introduction
Both the DCD1 and DCD2 converters on ISL9305 use the
peak-current-mode pulse-width modulation (PWM) control scheme
for fast transient response and pulse-by-pulse current limiting.
Both converters are able to supply up to 800mA load current. The
default output voltage ranges from 0.8V to 3.6V depending on the
factory pre-set configuration and can be programmed via the I
interface in the range of 0.825V to 3.6V at 25mV/step with a
programmable slew rate. An open-drain DCDPG (DCD Power-Good)
signal is also provided to monitor the DCD1 and DCD2 output
voltages. Optionally, both DCD1 and DCD2 can be programmed to
be actively discharged via an on-chip bleeding resistor (typical
115Ω) when the converter is disabled.
Skip Mode (PFM Mode) for DCD1/DCD2
Under light load condition, the DCD1 and DCD2 can be
programmed to automatically enter a pulse-skipping mode to
minimize the switching loss by reducing the switching frequency.
Figure 2 illustrates the skip mode operation. A zero-cross sensing
circuit monitors the current flowing through the SW node for zero
crossing. When it is detected to cross zero for 16 consecutive
CLOCK
V
OUT
I
L
0
7
16 CYCLES
v
v
EAMP
v
OUT
CSA
FIGURE 2. SKIP MODE OPERATION WAVEFORMS
d
i
L
FIGURE 3. PWM OPERATION WAVEFORMS
20% PEAK CURRENT LIMIT
1.015*V
ISL9305
2
C
OUT_NOMINAL
V
OUT_NOMINAL
cycles, the regulator enters the skip mode. During the 16
consecutive cycles, the inductor current could be negative. The
counter is reset to zero when the sensed current flowing through
the SW node does not cross zero during any cycle within the 16
consecutive cycles. Once the converter enters the skip mode, the
pulse modulation is controlled by an internal comparator while
each pulse cycle remains synchronized to the PWM clock. The
P-Channel MOSFET is turned on at the rising edge of the clock
and turned off when its current reaches ~20% of the peak
current limit. As the average inductor current in each cycle is
higher than the average current of the load, the output voltage
rises cycle-over-cycle. When the output voltage is sensed to reach
1.5% above its nominal voltage, the P-Channel MOSFET is turned
off immediately and the inductor current is fully discharged to
zero and stays at zero. The output voltage reduces gradually due
to the load current discharging the output capacitor. When the
output voltage drops to the nominal voltage, the P-Channel
MOSFET will be turned on again, repeating the previous
operations.
The regulator resumes normal PWM mode operation when the
output voltage is sensed to drop below 1.5% of its nominal
voltage value as shown in Figure 3.
November 8, 2010
FN7605.0