LFE2M20E-6FN256C Lattice, LFE2M20E-6FN256C Datasheet - Page 17
LFE2M20E-6FN256C
Manufacturer Part Number
LFE2M20E-6FN256C
Description
FPGA - Field Programmable Gate Array 19K LUTs 140 I/O SERDES DSP -6
Manufacturer
Lattice
Datasheet
1.LFE2-12SE-6FN256C.pdf
(389 pages)
Specifications of LFE2M20E-6FN256C
Number Of Macrocells
19000
Maximum Operating Frequency
357 MHz
Number Of Programmable I/os
140
Data Ram Size
1246208
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2M20E-6FN256C
Manufacturer:
Lattice
Quantity:
710
Company:
Part Number:
LFE2M20E-6FN256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Company:
Part Number:
LFE2M20E-6FN256C-5I
Manufacturer:
NATIONAL
Quantity:
633
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Lattice Semiconductor
Edge Clock Sources
Edge clock resources can be driven from a variety of sources at the same edge. Edge clock resources can be
driven from adjacent edge clock PIOs, primary clock PIOs, PLLs/DLLs and clock dividers as shown in Figure 2-12.
Figure 2-12. Edge Clock Sources
From Routing
From Routing
Sources for left edge clocks
Input
Input
DLL
PLL
Clock
Clock
Input
Input
DLLDELA
GPLL
DLL
Routing
Routing
From
From
Eight Edge Clocks (ECLK)
Two Clocks per Edge
Clock Input
Clock Input
2-14
Clock Input
Clock Input
Routing
Routing
From
From
Sources for top
LatticeECP2/M Family Data Sheet
bottom edge
Sources for
edge clocks
clocks
Sources for right edge clocks
GPLL
DLL
DLLDELA
Architecture
From Routing
From Routing
Clock
Clock
Input
Input
Input
Input
DLL
PLL
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