AGLN015V2-QNG68 Actel, AGLN015V2-QNG68 Datasheet - Page 75
AGLN015V2-QNG68
Manufacturer Part Number
AGLN015V2-QNG68
Description
FPGA - Field Programmable Gate Array 15K System Gates IGLOO nano
Manufacturer
Actel
Datasheet
1.AGLN030V5-ZUCG81.pdf
(140 pages)
Specifications of AGLN015V2-QNG68
Processor Series
AGLN015
Core
IP Core
Number Of Macrocells
128
Maximum Operating Frequency
250 MHz
Number Of Programmable I/os
49
Supply Voltage (max)
1.5 V
Supply Current
6 uA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 20 C
Development Tools By Supplier
AGLN-Nano-Kit, AGLN-Z-Nano-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FLASHPRO 4, FlashPro 3, FLASHPRO LITE
Mounting Style
SMD/SMT
Supply Voltage (min)
1.2 V
Number Of Gates
15 K
Package / Case
QFN-68
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Figure 2-24 • Timing Model and Waveforms
Table 2-87 • Register Delays
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
CLKQ
SUD
HD
SUE
HE
CLR2Q
PRE2Q
REMCLR
RECCLR
REMPRE
RECPRE
WCLR
WPRE
CKMPWH
CKMPWL
CLK
Data
EN
Out
PRE
CLR
For specific junction temperature and voltage supply levels, refer to
Timing Characteristics
1.5 V DC Core Voltage
Commercial-Case Conditions: T
Clock-to-Q of the Core Register
Data Setup Time for the Core Register
Data Hold Time for the Core Register
Enable Setup Time for the Core Register
Enable Hold Time for the Core Register
Asynchronous Clear-to-Q of the Core Register
Asynchronous Preset-to-Q of the Core Register
Asynchronous Clear Removal Time for the Core Register
Asynchronous Clear Recovery Time for the Core Register
Asynchronous Preset Removal Time for the Core Register
Asynchronous Preset Recovery Time for the Core Register
Asynchronous Clear Minimum Pulse Width for the Core Register
Asynchronous Preset Minimum Pulse Width for the Core Register
Clock Minimum Pulse Width HIGH for the Core Register
Clock Minimum Pulse Width LOW for the Core Register
50%
50%
t
SUE
t
HE
50%
t
CLKQ
50%
t
SUD
0
t
HD
t
PRE2Q
50%
50%
50%
t
J
WPRE
= 70°C, Worst-Case VCC = 1.425 V
50%
Description
50%
50%
t
t
RECPRE
R ev i si o n 1 1
WCLR
50%
t
50%
50%
CLR2Q
50%
t
RECCLR
Table 2-6 on page 2-6
IGLOO nano Low Power Flash FPGAs
50%
t
CKMPWH
t
50%
REMPRE
t
for derating values.
CKMPWL
50%
0.89
0.81
0.00
0.73
0.00
0.60
0.62
0.00
0.24
0.00
0.23
0.30
0.30
0.56
0.56
Std.
50%
50%
t
REMCLR
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2- 61
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