LFXP6C-4TN144I Lattice, LFXP6C-4TN144I Datasheet - Page 86
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LFXP6C-4TN144I
Manufacturer Part Number
LFXP6C-4TN144I
Description
FPGA - Field Programmable Gate Array 5.8K LUTs 100 IO 1.8 /2.5/3.3V -4 Spd I
Manufacturer
Lattice
Specifications of LFXP6C-4TN144I
Number Of Programmable I/os
100
Data Ram Size
73728
Supply Voltage (max)
3.465 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.71 V
Package / Case
TQFP-144
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP6C-4TN144I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
LFXP15 & LFXP20 Logic Signal Connections: 256 fpBGA (Cont.)
Number
Ball
M6
M3
M7
M8
N1
N2
N3
R4
N5
R1
N6
R2
R3
R5
N7
R6
N8
R7
K4
K5
P1
P2
P4
P3
P5
T2
T3
T4
T5
P6
T6
P7
L4
L5
-
-
-
-
-
-
-
-
SLEEPN
Function
GNDIO6
GNDIO6
GNDIO6
GNDIO5
GNDIO5
GNDIO5
GNDIO5
GNDIO5
PB11A
PB11B
PB12A
PB12B
PB13A
PB14B
PB15A
PB15B
PB16A
PB16B
PB17A
PB17B
PB18A
PB18B
PB19A
PB19B
PB20A
PB20B
PB21A
PB22B
PB23A
PL32A
PL33A
PL33B
PL35A
PL36B
PL37A
PL37B
PL38A
PL38B
PL39A
PL39B
INITN
Ball
1
/TOE
2
Bank Differential
6
6
6
6
6
6
6
6
6
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
-
LFXP15
C
C
T
T
C
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T
T
T
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3
3
3
3
LLM0_PLLC_FB_A
LLM0_PLLT_FB_A
VREF2_6
VREF1_5
VREF2_5
Function
Dual
DQS
DQS
DQS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
4-27
SLEEPN
Function
GNDIO6
GNDIO6
GNDIO6
GNDIO5
GNDIO5
GNDIO5
GNDIO5
GNDIO5
PB15A
PB15B
PB16A
PB16B
PB17A
PB18B
PB19A
PB19B
PB20A
PB20B
PB21A
PB21B
PB22A
PB22B
PB23A
PB23B
PB24A
PB24B
PB25A
PB26B
PB27A
PL36A
PL37A
PL37B
PL39A
PL40B
PL41A
PL41B
PL42A
PL42B
PL43A
PL43B
INITN
Ball
1
/TOE
2
Bank Differential
LatticeXP Family Data Sheet
6
6
6
6
6
6
6
6
6
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
-
LFXP20
C
C
T
T
C
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T
T
T
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3
3
3
3
Pinout Information
LLM0_PLLC_FB_A
LLM0_PLLT_FB_A
VREF2_6
VREF1_5
VREF2_5
Function
Dual
DQS
DQS
DQS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
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