A3P125-TQG144 Actel, A3P125-TQG144 Datasheet - Page 101
A3P125-TQG144
Manufacturer Part Number
A3P125-TQG144
Description
FPGA - Field Programmable Gate Array 125K System Gates
Manufacturer
Actel
Datasheet
1.A3P1000-FGG144.pdf
(218 pages)
Specifications of A3P125-TQG144
Processor Series
A3P125
Core
IP Core
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
133
Data Ram Size
36864
Delay Time
11.1 ns
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
125 K
Package / Case
TQFP-144
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A3P125-TQG144
Manufacturer:
ACTEL
Quantity:
204
Part Number:
A3P125-TQG144
Manufacturer:
ACTEL/爱特
Quantity:
20 000
Company:
Part Number:
A3P125-TQG144I
Manufacturer:
ACT
Quantity:
118
Company:
Part Number:
A3P125-TQG144I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
A3P125-TQG144I
Manufacturer:
MICROSEMI/美高森美
Quantity:
20 000
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Global Resource Characteristics
Figure 2-27 • Example of Global Tree Use in an A3P250 Device for Clock Routing
CCC
A3P250 Clock Tree Topology
Clock delays are device-specific.
global tree presented in
is used to drive all D-flip-flops in the device.
Figure 2-27
Figure 2-27
is driven by a CCC located on the west side of the A3P250 device. It
R e v i s i o n 9
is an example of a global tree used for clock routing. The
ProASIC3 Flash Family FPGAs
Central
Global Rib
VersaTile
Rows
Global Spine
2- 87
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