AGLN010V2-QNG48 Actel, AGLN010V2-QNG48 Datasheet - Page 79
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AGLN010V2-QNG48
Manufacturer Part Number
AGLN010V2-QNG48
Description
FPGA - Field Programmable Gate Array 10K System Gates IGLOO nano
Manufacturer
Actel
Datasheet
1.AGLN030V5-ZUCG81.pdf
(140 pages)
Specifications of AGLN010V2-QNG48
Processor Series
AGLN010
Core
IP Core
Number Of Macrocells
86
Maximum Operating Frequency
250 MHz
Number Of Programmable I/os
34
Supply Voltage (max)
1.5 V
Supply Current
3 uA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 20 C
Development Tools By Supplier
AGLN-Nano-Kit, AGLN-Z-Nano-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FLASHPRO 4, FlashPro 3, FLASHPRO LITE
Mounting Style
SMD/SMT
Supply Voltage (min)
1.2 V
Number Of Gates
10 K
Package / Case
QFN-48
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AGLN010V2-QNG48I
Manufacturer:
ACTEL10
Quantity:
4 142
Table 2-91 • AGLN020 Global Resource
Table 2-92 • AGLN060 Global Resource
Parameter
t
t
t
t
t
F
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
3. For specific junction temperature and voltage supply levels, refer to
Parameter
t
t
t
t
t
F
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
3. For specific junction temperature and voltage supply levels, refer to
RCKL
RCKH
RCKMPWH
RCKMPWL
RCKSW
RCKL
RCKH
RCKMPWH
RCKMPWL
RCKSW
RMAX
RMAX
located in a lightly loaded row (single element is connected to the global net).
loaded row (all available flip-flops are connected to the global net in the row).
located in a lightly loaded row (single element is connected to the global net).
loaded row (all available flip-flops are connected to the global net in the row).
Commercial-Case Conditions: T
Commercial-Case Conditions: T
Input Low Delay for Global Clock
Input High Delay for Global Clock
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
Maximum Frequency for Global Clock
Input Low Delay for Global Clock
Input High Delay for Global Clock
Minimum Pulse Width HIGH for Global Clock
Minimum Pulse Width LOW for Global Clock
Maximum Skew for Global Clock
Maximum Frequency for Global Clock
Description
Description
J
J
= 70°C, VCC = 1.425 V
= 70°C, VCC = 1.425 V
R ev i si o n 1 1
Table 2-6 on page 2-6
Table 2-6 on page 2-6
IGLOO nano Low Power Flash FPGAs
for derating values.
for derating values.
Min.
Min.
1.21
1.23
1.32
1.34
1
1
Std.
Std.
Max.
Max.
1.55
1.65
0.42
1.62
1.71
0.38
2
2
Units
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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