A3P250L-VQG100 Actel, A3P250L-VQG100 Datasheet - Page 136
A3P250L-VQG100
Manufacturer Part Number
A3P250L-VQG100
Description
FPGA - Field Programmable Gate Array 2.5K SYSTEM GATES
Manufacturer
Actel
Datasheet
1.A3P250L-VQG100.pdf
(224 pages)
Specifications of A3P250L-VQG100
Processor Series
A3P250
Core
IP Core
Maximum Operating Frequency
781.25 MHz
Number Of Programmable I/os
68
Data Ram Size
36864
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
250 K
Package / Case
VQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A3P250L-VQG100
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
A3P250L-VQG100I
Manufacturer:
Microsemi SoC
Quantity:
10 000
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ProASIC3L DC and Switching Characteristics
2- 12 2
Global Tree Timing Characteristics
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not
include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven
and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer
to the
present minimum and maximum global clock delays within each device. Minimum and maximum delays
are measured with minimum and maximum loading.
Timing Characteristics
Table 2-198 • A3P250L Global Resource – Applies to 1.5 V DC Core Voltage
Table 2-199 • A3P250L Global Resource – Applies to 1.2 V DC Core Voltage
Parameter
t
t
t
t
t
F
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
3. For specific junction temperature and voltage supply levels, refer to
Parameter
t
t
t
t
t
F
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
3. For specific junction temperature and voltage supply levels, refer to
RCKL
RCKH
RCKMPWH
RCKMPWL
RCKSW
RCKL
RCKH
RCKMPWH
RCKMPWL
RCKSW
RMAX
RMAX
element, located in a lightly loaded row (single element is connected to the global net).
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
values.
element, located in a lightly loaded row (single element is connected to the global net).
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
values.
"Clock Conditioning Circuits" section on page
Input Low Delay for Global Clock
Input High Delay for Global Clock
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
Maximum Frequency for Global Clock
Input Low Delay for Global Clock
Input High Delay for Global Clock
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
Maximum Frequency for Global Clock
Commercial-Case Conditions: T
Commercial-Case Conditions: T
Description
Description
R e visio n 9
J
J
= 70°C, VCC = 1.425 V
= 70°C, VCC = 1.14 V
2-126.
Table 2-198
Min.
Min.
0.82
0.80
1.40
1.38
Table 2-6 on page 2-7
Table 2-6 on page 2-7
1
1
to
–1
–1
Max.
Max.
1.06
1.09
0.29
1.68
1.71
0.33
Table 2-204 on page 2-125
2
2
Min.
Min.
0.96
0.94
1.64
1.62
Std.
1
Std.
1
Max.
Max.
1.25
1.28
0.34
1.97
2.01
0.39
for derating
for derating
2
2
Units
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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