ispPAC-POWR607-01SN32I Lattice, ispPAC-POWR607-01SN32I Datasheet - Page 23
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ispPAC-POWR607-01SN32I
Manufacturer Part Number
ispPAC-POWR607-01SN32I
Description
Supervisory Circuits Prec Prog Pwr Supply Seq Mon IND
Manufacturer
Lattice
Type
Power Supply Sequencer and Monitorr
Series
ispPAC®r
Datasheet
1.ISPPAC-POWR607-01SN32I.pdf
(28 pages)
Specifications of ispPAC-POWR607-01SN32I
Internal Hysteresis
Yes
Minimum Operating Temperature
- 40 C
Output Type
Open Collector / Drain
Power Fail Detection
Yes
Number Of Voltages Monitored
6
Monitored Voltage
Adj V
Undervoltage Threshold
Adj
Overvoltage Threshold
Adj
Manual Reset
Resettable
Watchdog
Yes
Power-up Reset Delay (typ)
100 us
Supply Voltage (max)
3.96 V
Supply Voltage (min)
2.64 V
Supply Current (typ)
3.5 mA
Mounting Style
SMD/SMT
Maximum Operating Temperature
+ 85 C
Package / Case
QFN-32
Applications
General Purpose
Voltage - Input
-0.3 V ~ 5.9 V
Voltage - Supply
2.64 V ~ 3.96 V
Current - Supply
3.5mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ISPPAC-POWR607-01SN32I
Manufacturer:
LATTICE
Quantity:
284
Part Number:
ISPPAC-POWR607-01SN32I
Manufacturer:
LATTICE
Quantity:
20 000
Lattice Semiconductor
Figure 4-19. ispPAC-POWR607 ID Code
ispPAC-POWR607 Specific Instructions
There are 25 unique instructions specified by Lattice for the ispPAC-POWR607. These instructions are primarily
used to interface to the various user registers and the E
used to control or monitor other features of the device. A brief description of each unique instruction is provided in
detail below, and the bit codes are found in Table 4-5.
PLD_ADDRESS_SHIFT – This instruction is used to set the address of the PLD AND/ARCH arrays for subsequent
program or read operations. This instruction also forces the outputs into the OUTPUTS_HIGHZ.
PLD_DATA_SHIFT – This instruction is used to shift PLD data into the register prior to programming or reading.
This instruction also forces the outputs into the OUTPUTS_HIGHZ.
PLD_INIT_ADDR_FOR_PROG_INCR – This instruction prepares the PLD address register for subsequent
PLD_PROG_INCR or PLD_VERIFY_INCR instructions.
PLD_PROG_INCR – This instruction programs the PLD data register for the current address and increments the
address register for the next set of data.
PLD_PROGRAM – This instruction programs the selected PLD AND/ARCH array column. The specific column is
preselected by using PLD_ADDRESS_SHIFT instruction. The programming occurs at the second rising edge of
the TCK in Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAM_ENABLE
instruction). This instruction also forces the outputs into the OUTPUTS_HIGHZ.
PROGRAM_SECURITY – This instruction is used to program the electronic security fuse (ESF) bit. Programming
the ESF bit protects proprietary designs from being read out. The programming occurs at the second rising edge of
the TCK in Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAM_ENABLE
instruction). This instruction also forces the outputs into the OUTPUTS_HIGHZ.
PLD_VERIFY – This instruction is used to read the content of the selected PLD AND/ARCH array column. This
specific column is preselected by using PLD_ADDRESS_SHIFT instruction. This instruction also forces the outputs
into the OUTPUTS_HIGHZ.
DISCHARGE – This instruction is used to discharge the internal programming supply voltage after an erase or pro-
gramming cycle and prepares ispPAC-POWR607 for a read cycle. This instruction also forces the outputs into the
OUTPUTS_HIGHZ.
BULK_ERASE – This instruction will bulk erase all E
POWR607. The device must already be in programming mode (PROGRAM_ENABLE instruction). This instruction
also forces the outputs into the OUTPUTS_HIGHZ.
OUTPUTS_HIGHZ – This instruction turns off all of the open-drain output transistors. Pins that are programmed as
FET drivers will be placed in the active low state. This instruction is effective after Update-Instruction-Register
JTAG state.
PROGRAM_ENABLE – This instruction enables the programming mode of the ispPAC-POWR607. This instruction
also forces the outputs into the OUTPUTS_HIGHZ.
00147h = ispPAC-POWR607
MSB
0000 0000 0001 0100 0111 / 0000 0100 001 / 1
Part Number
(20 bits)
Lattice Semiconductor
JEDEC Manufacturer
Identity Code for
(11 bits)
4-23
2
CMOS bits (CFG, PLD, UES, and ESF) in the ispPAC-
2
CMOS non-volatile memory. Additional instructions are
LSB
per 1149.1-1990
Constant 1
(ispPAC-POWR607)
(1 bit)
ispPAC-POWR607 Data Sheet