XR17V352IB-0A-EVB Exar Corporation, XR17V352IB-0A-EVB Datasheet - Page 39

• Manufacturer Part Number: XR17V352IB-0A-EVB
• Description: EVAL BOARD FOR XR17V352 113BGA
• Manufacturer: Exar Corporation

Specifications of XR17V352IB-0A-EVB

• Main Purpose: Interface, UART
• Embedded: -
• Utilized Ic / Part: XR17V352
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

A
REV. 1.0.1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 0 1
0 0 1 0
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
A3-A0
T
DDRESS
ABLE
13: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION.
FCTR
N
RHR
MCR
MSR
MSR
THR
DLM
FCR
SPR
DLD
LCR
LSR
R
DLL
IER
ISR
AME
EG
W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EAD
W
W
RITE
W
R
R
R
R
/
RX FIFO
RX FIFO
Polarity
Trigger
RS485
Enable
Enable
Divisor
Enable
RS485
B
BIT [7]
BIT [7]
BIT [7]
BIT [7]
DLY[3]
FIFOs
DSR#
Invert
Bit [7]
Pres-
Table
CTS/
BRG
caler
Error
Bit [1]
TRG
IT
Int.
CD
0/
0/
[7]
RX FIFO
Enable
Enable
Trigger
Set TX
Enable
RS485
B
BIT [6]
BIT [6]
BIT [6]
BIT [6]
DLY[2]
FIFOs
Empty
mode
DTR#
Break
Bit [6]
Bit [0]
Multi-
Table
RTS/
TRG
drop
TSR
IT
Int.
IR
RI
0/
0/
[6]
Char. Int.
TX FIFO
Set Par-
Xoff/Sp.
XonAny
Trigger
Enable
RS485
DLY[1]
RS485
Enable
B
Empty
XOFF
check
Delta-
Bit [5]
Bit [5]
Bit [5]
Bit [5]
XON/
parity
Bit [5]
Xon/
Flow
THR
DSR
Auto
Cntl
IT
ity
0/
0/
0/
0/
[5]
Even Par-
Loopback
RX Break
Xoff/spe-
RX Input
TX FIFO
Invert IR
cial char
39
Internal
Fast IR
Trigger
Enable
RS485
B
DLY[0]
Bit [4]
Bit [4]
Bit [4]
Bit [4]
mode
Bit [4]
CTS
HIGH PERFORMANCE DUAL PCI EXPRESS UART
IT
ity
0/
0/
0
[4]
Framing
Immedi-
TX char
Modem
Disable
Source
Enable
Enable
(OP2)
B
Status
Bit [3]
Bit [3]
Bit [3]
Bit [3]
Bit [3]
Bit [3]
Mode
Parity
Bit [3]
Bit [3]
Delta
DMA
Error
RTS/
DTR
CD#
Hyst
INT
IT
Int.
ate
RX
TX
[3]
1
Stop Bits
TX FIFO
Flow Sel
RX Line
RX Par-
ity Error
Disable
Enable
Source
(OP1)
B
Status
Bit [2]
Bit [2]
Bit [2]
Bit [2]
Bit [2]
Bit [2]
Reset
Bit [2]
Bit [2]
RTS/
Delta
RTS/
DTR
DTR
Hyst
INT
RI#
IT
Int.
RX
[2]
1
S
HADED BITS ARE ENABLED BY
RX FIFO
TX mode
Pin Con-
Overrun
Disable
Source
Enable
Length
Empty
B
Bit [1]
Bit [1]
Bit [1]
Reset
Bit [1]
DSR#
Bit [1]
Bit [1]
Bit [1]
Bit [1]
RTS#
Bit [1]
Word
Delta
RTS/
DTR
Hyst
INT
Int.
trol
RX
IT
TX
[1]
RX mode
RX Data
Pin Con-
RX Data
Disable
Enable
Source
Enable
Length
B
Ready
FIFOs
Bit [0]
Bit [0]
Bit [0]
Bit [0]
Bit [0]
Bit [0]
Bit [0]
DTR#
CTS#
Bit [0]
Bit [0]
Word
Delta
RTS/
DTR
Hyst
INT
IT
Int.
trol
XR17V352
[0]
User Data
EFR B
LCR[7]=0
LCR[7]=0
LCR[7]=1
LCR[7]=1
LCR[7]=1
LCR[7]=0
LCR[7]=0
LCR[7]=0
C
OMMENT
IT
-4.