SI4030-B1-FMR Silicon Laboratories Inc, SI4030-B1-FMR Datasheet

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... The Si4030/31/32 offers advanced radio features including continuous frequency coverage from 240–960 MHz with adjustable power output levels of –8 to +13 dBm on the Si4030/31 and +1 to +20 dBm on the Si4032. Power adjustments are made steps. The Si4030/31/32’s high level of integration offers reduced BOM cost while simplifying the overall system design. The Si4032’ ...

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... Si4030/31/32-B1 Functional Block Diagram 2 Rev 1.1 ...

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... General Purpose ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.4. Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 7.5. Low Battery Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 7.6. Wake-Up Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.7. GPIO Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8. Reference Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 9. Application Notes and Reference Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10. Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11. Register Table and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12. Pin Descriptions: Si4030/31/ 13. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Si4030/31/32-B1 Rev 1.1 Page 3 ...

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... Si4030/31/32-B1 14. Package Markings (Top Marks 14.1. Si4030/31/32 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 14.2. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 15. Package Outline: Si4030/31/ 16. PCB Land Pattern: Si4030/31/ Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 4 Rev 1.1 ...

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... Figure 15. Manchester Coding Example ...................................................................................37 Figure 16. POR Glitch Parameters............................................................................................ 39 Figure 17. General Purpose ADC Architecture ......................................................................... 41 Figure 18. Temperature Ranges using ADC8 ........................................................................... 43 Figure 19. WUT Interrupt and WUT Operation.......................................................................... 46 Figure 20. Si4031 Reference Design Schematic ...................................................................... 48 Figure 21. 20-Pin Quad Flat No-Lead (QFN) ............................................................................54 Figure 22. PCB Land Pattern .................................................................................................... 55 Si4030/31/32-B1 Rev 1.1 5 ...

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... Table 9. Serial Interface Timing Parameters ............................................................................15 Table 10. Operating Modes Response Time ............................................................................17 Table 11. Frequency Band Selection ....................................................................................... 23 Table 12. Packet Handler Registers ......................................................................................... 36 Table 13. POR Parameters ...................................................................................................... 39 Table 14. Temperature Sensor Range ..................................................................................... 42 Table 15. Register Descriptions ............................................................................................... 50 Table 16. Package Dimensions ................................................................................................ 54 Table 17. PCB Land Pattern Dimensions ................................................................................. 56 Si4030/31/32-B1 1 ...................................................................8 1 ...................................................................9 1 ...................................................................................10 Rev 1.1 6 ...

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... Using Silicon Labs’ Reference Design. TX current consumption is dependent on match and board layout. txpow[2:0] = 011 (+1 dBm) Using Silicon Labs’ Reference Design. TX current consumption is dependent on match and board layout. Rev 1.1 Si4030/31/32-B1 Min Typ Max Units 1.8 3.0 3.6 V — ...

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... Si4030/31/32-B1 Table 2. Synthesizer AC Electrical Characteristics Parameter Symbol Synthesizer Frequency F SYN Range—Si4031/32 Synthesizer Frequency F SYN Range—Si4030 Synthesizer Frequency F RES-LB 2 Resolution F RES-HB Reference Frequency f REF_LV 2 Input Level 2 Synthesizer Settling Time t LOCK 2 F Residual FM RMS 2 Phase Noise L(f M Notes: 1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are listed in the " ...

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... All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are listed in the "Production Test Conditions" section on page 13. 2. Guaranteed by qualification. Qualification test conditions are listed in the "Production Test Conditions" section on page 13. 3. Output power is dependent on matching components and board layout. Si4030/31/32-B1 1 Conditions 860–960 MHz 240–860 MHz controlled by txpow[2:0] – ...

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... Si4030/31/32-B1 Table 4. Auxiliary Block Specifications Parameter Symbol Temperature Sensor TS 2 Accuracy Temperature Sensor TS 2 Sensitivity Low Battery Detector LBD 2 Resolution Low Battery Detector LBD 2 Conversion Time Microcontroller Clock F MC Output Frequency General Purpose ADC ADC 2 Resolution General Purpose ADC Bit ADC ...

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... DRV<1:0>=LH OmaxLH I DRV<1:0>=HL OmaxHL I DRV<1:0>=HH OmaxHH V I < I source Omax V =1 < I sink Omax V =1 Rev 1.1 Si4030/31/32-B1 Min Typ Max Units — — 8 — — 8 — — – 0.6 — — DD — 0.6 –100 — 100 V – 0.6 — — DD — ...

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... Si4030/31/32-B1 Table 7. Absolute Maximum Ratings V to GND DD Instantaneous V to GND on TX Output Pin RF-peak Sustained V to GND on TX Output Pin RF-peak Voltage on Digital Control Inputs Voltage on Analog Inputs Operating Ambient Temperature Range T Thermal Impedance  JA Junction Temperature T J Storage Temperature Range T STG Note: Stresses beyond those listed under “ ...

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... DD TX output power measured at 915 MHz  External reference signal (XOUT) = 1.0 V  Production test schematic (unless noted otherwise)  All RF output levels referred to the pins of the Si4030/31/32 (not the RF module)  Qualification Test Conditions: = –40 to +85 °C T  +1.8 to +3.6 VDC  ...

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... MHz. The transmit FSK data is modulated directly into the  data stream and can be shaped by a Gaussian low-pass filter to reduce unwanted spectral content. The Si4032’s PA output power can be configured between +1 and +20 dBm steps, while the Si4030/31's PA output power can be configured between –8 and +13 dBm steps. The PA is single-ended to allow for easy antenna matching and low BOM cost ...

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... Select high period SW To read back data from the Si4030/31/32, the R/W bit must be set to 0 followed by the 7-bit address of the register from which to read. The 8 bit DATA field following the 7-bit ADDR field is ignored n the SDI pin when R The next eight negative edge transitions of the SCLK signal will clock out the contents of the selected register. The data read from the selected register will be available on the SDO output pin ...

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... SPI address. When the nSEL bit is held low while continuing to send SCLK pulses, the SPI interface will automatically increment the ADDR and read from/write to the next address. An example burst write transaction is illustrated in Figure 3 and a burst read in Figure 4. As long as nSEL is held low, input data will be latched into the Si4030/31/32 every eight SCLK cycles. First Bit RW ...

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... Operating Mode Control There are three primary states in the Si4030/31/32 radio state machine: SHUTDOWN, IDLE, and TX (see Figure 5). The SHUTDOWN state completely shuts down the radio to minimize current consumption. There are five different configurations/options for the IDLE state which can be selected to optimize the chip to the applications needs. " ...

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... Si4030/31/32-B1 3.2.1. SHUTDOWN State The SHUTDOWN state is the lowest current consumption state of the device with nominally less than current consumption. The SHUTDOWN state may be entered by driving the SDN pin (Pin 20) high. The SDN pin should be held low in all states except the SHUTDOWN state. In the SHUTDOWN state, the contents of the registers are lost and there is no SPI access ...

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... By default, the VCO and PLL are calibrated every time the PLL is enabled. 3.2.4. Device Status Add R/W Function/Description 02 R Device Status The operational status of the chip can be read from "Register 02h. Device Status" ffovfl ffunfl Reserved Reserved Rev 1.1 Si4030/31/32- POR Def. freqerr cps[1] cps[0] — 19 ...

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... Si4030/31/32-B1 3.3. Interrupts The Si4030/31/32 is capable of generating an interrupt signal when certain events occur. The chip notifies the microcontroller that an interrupt event has occurred by setting the nIRQ output pin LOW = 0. This interrupt signal will be generated when any one (or more) of the interrupt events (corresponding to the Interrupt Status bits) shown below occur. The nIRQ pin will remain low until the microcontroller reads the Interrupt Status Register(s) (Registers 03h– ...

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... PLL T0, PLL CAL, and PLL TS under all conditions is 200 µs. Under certain applications, the PLL T0 time and the PLL CAL may be skipped for faster turn-around time. Contact applications support if faster turnaround time is desired. XTAL Settling Time 600us Si4030/31/32-B1 TX Packet Figure 6. TX Timing Rev 1.1 21 ...

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... Frequency Programming In order to transmit an RF signal, the desired channel frequency, f Si4030/31/32. Note that this frequency is the center frequency of the desired channel. The carrier frequency is generated by a Fractional-N Synthesizer, using 10 MHz both as the reference frequency and the clock of the (3 order) ΔΣ modulator. This modulator uses modulo 64000 accumulators. This design was made to obtain the desired frequency resolution of the synthesizer ...

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... MHz 21 45 450–459.9 MHz 22 46 460–469.9 MHz 23 47 470–479.9 MHz Rev 1.1 Si4030/31/32-B1 Frequency Band hbsel=0 hbsel=1 480–499.9 MHz 500–519.9 MHz 520–539.9 MHz 540–559.9 MHz 560–579.9 MHz 580–599.9 MHz 600–619.9 MHz 620– ...

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... Si4030/31/32-B1 3.5.2. Easy Frequency Programming for FHSS While Registers 73h–77h may be used to program the carrier frequency of the Si4030/31/32 often easier to think in terms of “channels” or “channel numbers” rather than an absolute frequency value in Hz. Also, there may be some timing-critical applications (such as for Frequency Hopping Systems) in which it is desirable to change frequency by programming a single register. Once the channel step size is set, the frequency may be changed by a single register corresponding to the channel number. A nominal frequency is first set using Registers 73h– ...

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... Modulation Type" on page 27 for further details. Add R/W Function/Description 71 R/W Modulation Mode Control 2 trclk[1] trclk[0] dtmod[1] dtmod[0] eninv fd[8] modtyp[1] modtyp[0] 72 R/W Frequency Deviation f f carrier Time Figure 7. Frequency Deviation fd[7] fd[6] fd[5] fd[4] fd[3] Rev 1.1 Si4030/31/32- POR Def. 00h fd[2] fd[1] fd[0] 20h 25 ...

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... Si4030/31/32-B1 3.5.5. Frequency Offset Adjustment A frequency offset can be adjusted manually by fo[9:0] in registers 73h and 74h. The frequency offset adjustment is implemented by shifting the Synthesizer Local Oscillator frequency. This register is a signed register so in order to get a negative offset it is necessary to take the twos complement of the positive offset number. The offset can be ...

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... Modulation Options 4.1. Modulation Type The Si4030/31/32 supports three different modulation options: Gaussian Frequency Shift Keying (GFSK), Frequency Shift Keying (FSK), and On-Off Keying (OOK). GFSK is the recommended modulation type as it provides the best performance and cleanest modulation spectrum. Figure 8 demonstrates the difference between FSK and GFSK for a Data Rate of 64 kbps ...

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... Si4030/31/32-B1 4.2. Modulation Data Source The Si4030/31/32 may be configured to obtain its modulation data from one of three different sources: FIFO mode, Direct Mode, and from a PN9 mode. In Direct Mode, the TX modulation data may be obtained from several different input pins. These options are set through the dtmod[1:0] field in "Register 71h. Modulation Mode Control 2." ...

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... Gaussian lowpass filter function to apply to the incoming data. One advantage of this mode that it saves a microcontroller pin because no TX Clock output function is required. The primary disadvantage of this mode is the increase in occupied spectral bandwidth with FSK (as compared to GFSK). Si4030/31/32-B1 TX Data Clock Configuration Rev 1.1 29 ...

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... Si4030/31/32-B1 4.2.2.3. Direct Mode using SPI or nIRQ Pins In certain applications it may be desirable to minimize the connections to the microcontroller or to preserve the GPIOs for other uses. For these cases it is possible to use the SPI pins and nIRQ as the modulation clock and data. The SDO pin can be configured to be the data clock by programming trclk = 10. If the nSEL pin is LOW then the function of the pin will be SPI data output ...

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... The Si4032 contains an internal integrated power amplifier (PA) capable of transmitting at output levels between –1 and +20 dBm. The Si4030/31 contains a PA which is capable of transmitting output levels between –8 to +13 dBm. The PA design is single-ended and is implemented as a two stage class CE amplifier with a high efficiency when transmitting at maximum power ...

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... However, depending on the duty cycle of the system, the effect on battery life may be insignificant. Contact Silicon Labs Support for help in evaluating this tradeoff. The +13 dBm output power of the Si4030/31 is targeted at systems that require lower output power. The PA still offers high efficiency and a range of output power from –8 to +13 dBm. ...

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... Capacitance 5.4. Regulators There are a total of four regulators integrated onto the Si4030/31/32. With the exception of the digital regulator, all regulators are designed to operate with only internal decoupling. The digital regulator requires an external 1 µF decoupling capacitor. All regulators are designed to operate with an input supply voltage from +1.8 to +3.6 V. The output stage of the not connected internally to a regulator and is connected directly to the battery voltage ...

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... Si4030/31/32-B1 6. Data Handling and Packet Handler The internal modem is designed to operate with a packet including a 10101... preamble structure. To configure the modem to operate with packet formats without a preamble or other legacy packet structures contact customer support. 6.1. TX FIFO A 64 byte FIFO is integrated into the chip for TX, as shown in Figure 11. "Register 7Fh. FIFO Access" is used to access the FIFO. A burst write, as described in " ...

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... CRC) can be configured to be automatically added to the data payload. The fields needed for packet generation normally change infrequently and can therefore be stored in registers. Automatically adding these fields to the data payload greatly reduces the amount of communication between the microcontroller and the Si4030/31/32 and reduces the required computational power of the microcontroller. ...

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... Si4030/31/32-B1 D ata 1 D ata 2 D ata 3 D ata 4 D ata 5 D ata 6 D ata 7 D ata 8 D ata 9 Figure 13. Multiple Packets in TX Packet Handler Add R/W Function/Description D7 30 R/W Data Access Control Reserved 31 R EzMAC status 32 33 R/W Header Control 2 skipsyn ...

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... First 4bits of the synch. word = 0x2 First 4bits of the synch. word = 0x2 Rev 1.1 Si4030/31/32-B1 CRC Data before Manchester Data after Machester ( manppol = 1, enmaninv = 0) Data after Machester ( manppol = 1, enmaninv = 1) Data before Manchester Data after Machester ( manppol = 0, enmaninv = 0) Data after Machester ( manppol = 0, enmaninv = 1) 37 ...

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... Si4030/31/32-B1 6.6. TX Retransmission and Auto TX The Si4030/31/32 is capable of automatically retransmitting the last packet loaded in the TX FIFO. Automatic retransmission is set by entering the TX state with the txon bit without reloading the TX FIFO. This feature is useful for beacon transmission or when retransmission is required due to the absence of a valid acknowledgement. Only packets that fit completely in the TX FIFO can be automatically retransmitted ...

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... Auxiliary Functions 7.1. Smart Reset The Si4030/31/32 contains an enhanced integrated SMART RESET or POR circuit. The POR circuit contains both a classic level threshold reset as well as a slope detector POR. This reset circuit was designed to produce a reliable reset signal under any circumstances. Reset will be initiated if any of the following conditions occur: Initial power on, VDD starts from gnd: reset is active till V  ...

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... If the microcontroller clock option is being used there may be the need of a system clock for the microcontroller while the Si4030/31/ SLEEP mode. Since the crystal oscillator is disabled in SLEEP mode in order to save current, the low-power 32.768 kHz clock can be automatically switched to become the microcontroller clock. This feature is called enable low frequency clock and is enabled by the enlfc bit in “ ...

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... V in adcsel [2:0] V ref Ref MUX adcref [1: adcsel[2] adcsel[1] adcsel[0] adcref[1] soffs[3] adc[7] adc[6] adc[5] adc[4] adc[3] Rev 1.1 Si4030/31/32- /3. A programmable 8-bit ADC adc [7:0] 0 -1020mV / 0-255 POR Def. adcref[0] adcgain[1] adcgain[0] 00h soffs[2] soffs[1] soffs[0] 00h adc[2] adc[1] adc[0] — ...

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... Si4030/31/32-B1 7.4. Temperature Sensor An integrated on-chip analog temperature sensor is available. The temperature sensor will be automatically enabled when the temperature sensor is selected as the input of the ADC or when the analog temp voltage is selected on the analog test bus. The temperature sensor value may be digitized using the general-purpose ADC and read out over the SPI through " ...

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... Temperature Measurement with ADC8 300 250 200 150 100 50 0 -40 - Temperature [Celsius] Figure 18. Temperature Ranges using ADC8 Si4030/31/32-B1 Sensor Range 0 Sensor Range 1 Sensor Range 2 Sensor Range 100 Rev 1.1 43 ...

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... Si4030/31/32-B1 7.5. Low Battery Detector A low battery detector (LBD) with digital read-out is integrated into the chip. A digital threshold may be programmed into the lbdt[4:0] field in "Register 1Ah. Low Battery Detector Threshold." When the digitized battery voltage reaches this threshold an interrupt will be generated on the nIRQ pin to the microcontroller. The microcontroller can confirm source of the interrupt by reading " ...

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... M Value in Formula wtr[3] wtr[2] wtr[1] wtm[7] wtm[6] wtm[5] wtm[4] wtm[3] wtv[15] wtv[14] wtv[13] wtv[12] wtv[11] wtv[7] wtv[6] wtv[5] wtv[4] wtv[3] Rev 1.1 Si4030/31/32- POR Def. wtr[0] wtd[1] wtd[0] 00h 00h wtm[2] wtm[1] wtm[0] 00h wtv[10] wtv[9] wtv[8] — wtv[2] wtv[1] wtv[0] — ...

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... Si4030/31/32-B1 WUT Period GPIOX =00001 nIRQ SPI Interrupt Read Chip State Sleep Ready 1.5 mA Current Consumption WUT Period GPIOX =00001 nIRQ SPI Interrupt Read Chip State Current Consumption Figure 19. WUT Interrupt and WUT Operation 46 Interrupt Enable enwut =1 ( Reg 06h) Sleep Ready 1 ...

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... GPIO 00000—Default Setting GPIO0 POR GPIO1 POR Inverted GPIO2 Microcontroller Clock Rev 1.1 Si4030/31/32- POR Def. 00h 00h 00h dio2 dio1 dio0 00h 47 ...

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... Si4030/31/32-B1 8. Reference Design Reference designs are available at schematics, BOM, and layout. TX matching component values for the different frequency bands can be found in the application notes “AN435: Si4032/4432 PA Matching” and “AN436: Si4030/4031/4430/4431 PA Matching.” 48 www.silabs.com for many common applications which include recommended ...

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... AN429: Using the DC-DC Converter on the F9xx Series MCU for Single Battery Operation with the  EZRadioPRO RF Devices AN432: RX BER Measurement on EZRadioPRO with a Looped PN Sequence  AN435: Si4032/4432 PA Matching  AN436: Si4030/4031/4430/4431 PA Matching  AN437: 915 MHz Measurement Results and FCC Compliance  AN439: EZRadioPRO Quick Start Guide  AN440: Si4430/31/32 Detailed Register Descriptions  ...

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... R/W Frequency Hopping Channel Select 7A R/W Frequency Hopping Step Size 7C R/W TX FIFO Control 1 7D R/W TX FIFO Control R/W FIFO Access Note: Detailed register descriptions are available in “AN466: Si4030/31/32 Register Descriptions.” 50 Table 15. Register Descriptions vc[4] ffovfl ffunfl Reserved ifferr itxffafull itxffaem ...

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... PKG PADDLE_GND GND The exposed metal paddle on the bottom of the Si4030/31/32 supplies the RF and circuit ground(s) for the entire chip very important that a good solder connection is made between this exposed metal paddle and the ground plane of the PCB underlying the Si4030/31/32. ...

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... Si4030/31/32-B1 13. Ordering Information Part Number* Si4030-B1-FM ISM EZRadioPRO Transmitter Si4031-B1-FM ISM EZRadioPRO Transmitter Si4032-B1-FM ISM EZRadioPRO Transmitter *Note: Add an “(R)” at the end of the device part number to denote tape and reel option; 2500 quantity per reel. 52 Description Rev 1.1 Package Operating ...

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... Package Markings (Top Marks) 14.1. Si4030/31/32 Top Mark 14.2. Top Mark Explanation YAG Laser Mark Method Part Number Line 1 Marking Die Revision Line 2 Marking: TTTTT = Internal Code YY= Year Line 3 Marking Workweek Si4030/31/32- Si4030 1 = Si4031 2 = Si4032 B = Revision B1 Internal tracking code. Assigned by the Assembly House. Corresponds to the last significant digit of the year and workweek of the mold date ...

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... Si4030/31/32-B1 15. Package Outline: Si4030/31/32 Figure 21 illustrates the package details for the Si4030/31/32. Table 16 lists the values for the dimensions shown in the illustration. Figure 21. 20-Pin Quad Flat No-Lead (QFN) Symbol aaa bbb ccc ddd eee Notes: 1. All dimensions are shown in millimeters (mm) unless otherwise noted. ...

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... PCB Land Pattern: Si4030/31/32 Figure 22 illustrates the PCB land pattern details for the Si4030/31/32. Table 17 lists the values for the dimensions shown in the illustration. Figure 22. PCB Land Pattern Rev 1.1 Si4030/31/32-B1 55 ...

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... Si4030/31/32-B1 Table 17. PCB Land Pattern Dimensions Symbol Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This land pattern design is based on IPC-7351 guidelines. Note: Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad µm minimum, all the way around the pad ...

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... OCUMENT HANGE IST Revision 1.0 to Revision 1.1 Corrected typo under Features/Low Power Consumption on page 1.  Si4030/31/32-B1 Rev 1.1 57 ...

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... Si4030/31/32- ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...