ADF7012BRUZ Analog Devices Inc, ADF7012BRUZ Datasheet
ADF7012BRUZ
Specifications of ADF7012BRUZ
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ADF7012BRUZ Summary of contents
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FEATURES Single-chip, low power UHF transmitter 75 MHz to 1 GHz frequency operation Multichannel operation using fractional-N PLL 2 3.6 V operation On-board regulator Programmable output power −16 dBm to +14 dBm, 0.4 dB steps Data rates: dc ...
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ADF7012 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Timing Characteristics ..................................................................... 5 Absolute Maximum Ratings ............................................................ 6 Transistor Count ........................................................................... 6 ESD ...
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SPECIFICATIONS DV = 2.3 V – 3.6 V; AGND = DGND = Table 1. Parameter RF OUTPUT CHARACTERISTICS Operating Frequency Phase Frequency Detector MODULATION PARAMETERS Data Rate FSK/GFSK Data Rate ASK/OOK Deviation FSK/GFSK GFSK BT ASK ...
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ADF7012 Parameter PHASE-LOCKED LOOP PARAMETERS VCO Gain 315 MHz 433 MHz 868 MHz 915 MHz VCO Tuning Range Spurious (IVCO Min/Max) Charge Pump Current Setting [00] Setting [01] Setting [10] Setting [11] 1 Phase Noise (In band) 315 MHz 433 ...
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TIMING CHARACTERISTICS ± 10%; AGND = DGND = Table 2. Parameter Limit MIN MAX ...
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ADF7012 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter DV to GND DD (GND = AGND = DGND = 0 V) Digital I/O Voltage to GND Analog I/O Voltage to GND Operating Temperature Range Maximum ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 4. Pin Functional Descriptions Pin No. Mnemonic Description 1 DV Positive Supply for the Digital Circuitry. This must be between 2.3 V and 3.6 V. Decoupling capacitors to the analog ground DD plane should ...
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ADF7012 TYPICAL PERFORMANCE CHARACTERISTICS 315 MHz –60 –70 –80 –90 –100 –110 –120 –130 –140 1.0k 10.0k 100.0k PHASE NOISE (Hz) Figure 4. Phase Noise Response— 2.0 mA 315 MHz, PFD = 3.6864 MHz, PA ...
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MHz 1 2.00V/ 2 1.00V/ 1.50ms 500μs TRIG'D 2 CLKOUT 1 CE Figure 10. Crystal Power-On Time, 4 MHz, Time = 1.6 ms –40 FREQUENCY = 393.38 kHz –60 LEVEL = –102.34dBc/Hz –80 –100 –120 –140 –160 –180 –200 ...
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ADF7012 868 MHz 0 FREQUENCY = 251.3 kHz –20 LEVEL = –99.39dBc/Hz –40 –60 –80 –100 –120 –140 –160 1.0k 10.0k 100.0k PHASE NOISE (Hz) Figure 16. Phase Noise Response—I = 2.5 mA 868.95 MHz, PFD ...
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MHz –40 FREQUENCY = 992.38 kHz –60 LEVEL = –102.34dBc/Hz –80 –100 –120 –140 –160 –180 –200 1.0k 10.0k 100.0k PHASE NOISE (Hz) Figure 21. Phase Noise Response—I = 1.44 mA 915.2 MHz, PFD =10 ...
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ADF7012 CIRCUIT DESCRIPTION PLL OPERATION A fractional-N PLL allows multiple output frequencies to be generated from a single-reference oscillator (usually a crystal) simply by changing the programmable N value found in the N register. At the phase frequency detector (PFD), ...
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DV DD DIVIDER ÷2 OSC1 Figure 28. CLKOUT Stage The output buffer to CLK is enabled by setting Bit DB4 in OUT the function register high. On power-up, this bit is set high. The output buffer can ...
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ADF7012 PFD/ 4R CHARGE PUMP FSK DEVIATION FREQUENCY –F DEV THIRD-ORDER Σ-Δ MODULATOR +F DEV TxDATA FRACTIONAL-N Figure 30. FSK Implementation The deviation from the center frequency is set using the bits in the modulation register. The ...
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The nonlinear characteristic of the output stage results in an output spectrum containing harmonics of the fundamental, especially the third and fifth. To meet local regulations, a low- pass filter usually is required to filter these harmonics. The output stage ...
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ADF7012 OUTPUT DIVIDER An output divider is a programmable divider following the VCO in the PLL loop useful when using the ADF7012 to generate frequencies of < 500 MHz. REFERENCE LOOP PFD CP VCO DIVIDER FILTER ÷N Figure ...
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THEORY OF OPERATION CHOOSING THE EXTERNAL INDUCTOR VALUE The ADF7012 allows operation at many different frequencies by choosing the external VCO inductor to give the correct output frequency. Figure 36 shows both the minimum and maximum frequency vs. the inductor ...
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ADF7012 TIPS ON DESIGNING THE LOOP FILTER The loop filter design is crucial in ensuring stable operation of the transmitter, meeting adjacent channel power (ACP) specifications, and meeting spurious requirements for the relevant regulations. ADIsimSRD Design Studio™ free ...
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APPLICATION EXAMPLES Figure 40. Applications Diagram with Harmonic Filter Rev Page ADF7012 04617-0-035 ...
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ADF7012 315 MHz OPERATION The recommendations presented here are guidelines only. The design should be subject to internal testing prior to FCC site testing. Matching components need to be adjusted for board layout. The FCC standard 15.231 regulates operation in ...
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MHz OPERATION The recommendations here are guidelines only. The design should be subject to internal testing prior to ETSI site testing. Matching components need to be adjusted for board layout. The ETSI standard EN 300-220 governs operation in the ...
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ADF7012 868 MHz OPERATION The recommendations here are guidelines only. The design should be subject to internal testing prior to ETSI site testing. Matching components need to be adjusted for board layout. The ETSI standard EN 300-220 governs operation in ...
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MHz OPERATION The recommendations here are guidelines only. The design should be subject to internal testing prior to FCC site testing. Matching components need to be adjusted for board layout. FCC 15.247 and FCC 15.249 are the main regulations ...
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ADF7012 REGISTER DESCRIPTIONS REGISTER 0: R REGISTER OUTPUT VCO DIVIDER ADJUST OD2 OD1 OUTPUT DIVIDER 0 0 DISABLED 0 1 DIVIDE DIVIDE DIVIDE BY 8 VA2 VA1 VCO ADJUST ...
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REGISTER 1: N-COUNTER LATCH P1 PRESCALER 0 4/5 1 8/9 8-BIT INTEGER-N 12-BIT FRACTIONAL-N M12 M11 M10 ....... ....... ....... ....... ....... . . ...
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ADF7012 REGISTER 2: MODULATION REGISTER TEST BITS MUST BE LOW IC2 IC1 MC3 MC2 GFSK MOD MODULATION DEVIATION CONTROL IF AMPLITUDE SHIFT KEYING SELECTED, ...
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REGISTER 3: FUNCTION REGISTER SD TEST PLL TEST MODES MODES PA3 PA2 PA1 PA BIAS 5µ 6µ 7µ 12µA VCO ...
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... ADF7012BRU-REEL −40°C to +85°C 1 ADF7012BRU-REEL7 −40°C to +85°C ADF7012BRUZ 1 −40°C to +85°C 1 ADF7012BRUZ-RL −40°C to +85°C 1 ADF7012BRUZ-RL7 −40°C to +85°C 1 EVAL-ADF7012DBZ1 1 EVAL-ADF7012DBZ2 1 EVAL-ADF7012DBZ3 1 EVAL-ADF7012DBZ4 1 EVAL-ADF7012DBZ5 RoHS Compliant Part. ©2007–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...