ATMEGA1284PR212-MU Atmel, ATMEGA1284PR212-MU Datasheet - Page 82

• Manufacturer Part Number: ATMEGA1284PR212-MU
• Description: BUNDLE ATMEGA1284P/RF212 QFN
• Manufacturer: Atmel

Specifications of ATMEGA1284PR212-MU

• Frequency: 2.4GHz
• Modulation Or Protocol: 802.15.4 Zigbee, 6LoWPAN, ISM
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Package / Case: 44-QFN, 32-QFN
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Development Tools By Supplier: ATAVRRZ541, ATAVRRAVEN, ATAVRRZUSBSTICK, ATAVRISP2, ATAVRRZ201
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Power - Output: -
• Operating Temperature: -
• Applications: -
• Sensitivity: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Details

8059D–AVR–11/09
CLKO, Divided System Clock: The divided system clock can be output on the PB1 pin. The
divided system clock will be output if the CKOUT Fuse is programmed, regardless of the
PORTB1 and DDB1 settings. It will also be output during reset.
PCINT9, Pin Change Interrupt source 9: The PB1 pin can serve as an external interrupt source.
• T0/XCK0/PCINT8, Bit 0
T0, Timer/Counter0 counter source.
XCK0, USART0 External clock. The Data Direction Register (DDB0) controls whether the clock
is output (DDD0 set “one”) or input (DDD0 cleared). The XCK0 pin is active only when the
USART0 operates in Synchronous mode.
PCINT8, Pin Change Interrupt source 8: The PB0 pin can serve as an external interrupt source.
Table 12-7
shown in
MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. .
Table 12-7.
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Figure 12-5 on page
PB7/SCK/
OC3B/PCINT15
SPE • MSTR
PORTB7 • PUD
SPE • MSTR
0
SPE • MSTR
OC3B ENABLE
SCK OUTPUT
OC3B
PCINT15 • PCIE1
1
SCK INPUT
PCINT17 INPUT
–
and
Overriding Signals for Alternate Functions in PB7:PB4
Table 12-8
relate the alternate functions of Port B to the overriding signals
76. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the
PB6/MISO/
OC3A/PCINT14
SPE • MSTR
PORTB14 • PUD
SPE • MSTR
0
SPE • MSTR
OC3A ENABLE
SPI SLAVE OUTPUT
OC3A
PCINT14 • PCIE1
1
SPI MSTR INPUT
PCINT14 INPUT
–
PB5/MOSI/
ICP3/PCINT13
SPE • MSTR
PORTB13 • PUD
SPE • MSTR
0
SPE • MSTR
SPI MSTR OUTPUT
PCINT13 • PCIE1
1
SPI SLAVE INPUT
PCINT13 INPUT
ICP3 INPUT
–
ATmega1284P
PB4/SS/OC0B/
PCINT12
SPE • MSTR
PORTB12 • PUD
SPE • MSTR
0
OC0A ENABLE
OC0A
PCINT4 • PCIE1
1
SPI SS
PCINT12 INPUT
–
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