ATMEGA1284PR212-MU Atmel, ATMEGA1284PR212-MU Datasheet - Page 70

• Manufacturer Part Number: ATMEGA1284PR212-MU
• Description: BUNDLE ATMEGA1284P/RF212 QFN
• Manufacturer: Atmel

Specifications of ATMEGA1284PR212-MU

• Frequency: 2.4GHz
• Modulation Or Protocol: 802.15.4 Zigbee, 6LoWPAN, ISM
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Package / Case: 44-QFN, 32-QFN
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Development Tools By Supplier: ATAVRRZ541, ATAVRRAVEN, ATAVRRZUSBSTICK, ATAVRISP2, ATAVRRZ201
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Power - Output: -
• Operating Temperature: -
• Applications: -
• Sensitivity: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Details

12. I/O-Ports
12.1
8059D–AVR–11/09
Overview
All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports.
This means that the direction of one port pin can be changed without unintentionally changing
the direction of any other pin with the SBI and CBI instructions. The same applies when chang-
ing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as
input). Each output buffer has symmetrical drive characteristics with both high sink and source
capability. The pin driver is strong enough to drive LED displays directly. All port pins have indi-
vidually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have
protection diodes to both V
acteristics” on page 323
Figure 12-1. I/O Pin Equivalent Schematic
All registers and bit references in this section are written in general form. A lower case “x” repre-
sents the numbering letter for the port, and a lower case “n” represents the bit number. However,
when using the register or bit defines in a program, the precise form must be used. For example,
PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The physical I/O Regis-
ters and bit locations are listed in
Three I/O memory address locations are allocated for each port, one each for the Data Register
– PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins
I/O location is read only, while the Data Register and the Data Direction Register are read/write.
However, writing a logic one to a bit in the PINx Register, will result in a toggle in the correspond-
ing bit in the Data Register. In addition, the Pull-up Disable – PUD bit in MCUCR disables the
pull-up function for all pins in all ports when set.
Using the I/O port as General Digital I/O is described in
71. Most port pins are multiplexed with alternate functions for the peripheral features on the
device. How each alternate function interferes with the port pin is described in
Functions” on page
nate functions.
Pxn
76. Refer to the individual module sections for a full description of the alter-
for a complete list of parameters.
CC
and Ground as indicated in
”Register Description” on page
C
pin
”Ports as General Digital I/O” on page
Figure
"General Digital I/O" for
90.
12-1. Refer to
See Figure
R
Details
pu
ATmega1284P
Logic
”Electrical Char-
”Alternate Port
70