ATMEGA1284PR212-MU Atmel, ATMEGA1284PR212-MU Datasheet - Page 46

• Manufacturer Part Number: ATMEGA1284PR212-MU
• Description: BUNDLE ATMEGA1284P/RF212 QFN
• Manufacturer: Atmel

Specifications of ATMEGA1284PR212-MU

• Frequency: 2.4GHz
• Modulation Or Protocol: 802.15.4 Zigbee, 6LoWPAN, ISM
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Package / Case: 44-QFN, 32-QFN
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Development Tools By Supplier: ATAVRRZ541, ATAVRRAVEN, ATAVRRZUSBSTICK, ATAVRISP2, ATAVRRZ201
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Power - Output: -
• Operating Temperature: -
• Applications: -
• Sensitivity: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Details

8.12.2
8.12.3
8.12.4
8059D–AVR–11/09
MCUCR – MCU Control Register
PRR1 – Power Reduction Register 1
PRR0 – Power Reduction Register 0
• Bit 6 – BODS: BOD Sleep
The BODS bit must be written to logic one in order to turn off BOD during sleep, see
on page
BODSE in MCUCR. To disable BOD in relevant sleep modes, both BODS and BODSE must first
be set to one. Then, to set the BODS bit, BODS must be set to one and BODSE must be set to
zero within four clock cycles.
The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed
while BODS is active in order to turn off the BOD for the actual sleep mode. The BODS bit is
automatically cleared after three clock cycles.
• Bit 5 – BODSE: BOD Sleep Enable
BODSE enables setting of BODS control bit, as explained in BODS bit description. BOD disable
is controlled by a timed sequence.
• Bit 7:1 - Res: Reserved
• Bit 0 - PRTIM3: Power Reduction Timer/Counter3
Writing a logic one to this bit shuts down the Timer/Counter3 module. When the Timer/Counter3
is enabled, operation will continue like before the shutdown.
• Bit 7 - PRTWI: Power Reduction TWI
Writing a logic one to this bit shuts down the TWI by stopping the clock to the module. When
waking up the TWI again, the TWI should be re initialized to ensure proper operation.
• Bit 6 - PRTIM2: Power Reduction Timer/Counter2
Writing a logic one to this bit shuts down the Timer/Counter2 module in synchronous mode (AS2
is 0). When the Timer/Counter2 is enabled, operation will continue like before the shutdown.
Bit
0x35 (0x55)
Read/Write
Initial Value
Bit
(0x65)
Read/Write
Initial Value
Bit
(0x64)
Read/Write
Initial Value
40. Writing to the BODS bit is controlled by a timed sequence and an enable bit,
PRTWI
R/W
JTD
R/W
7
0
R
7
0
7
0
-
PRTIM2
R/W
BODS
6
0
R
R
6
0
6
0
-
PRTIM0
R/W
BODSE
5
0
R
5
0
R
-
5
0
PRUSART1
R/W
4
0
PUD
R/W
R
4
0
-
0
4
PRTIM1
R/W
R
3
0
-
3
0
R
3
–
0
PRSPI
R/W
2
0
R
R
2
0
2
–
0
-
ATmega1284P
PRUSART0
IVSEL
R/W
R/W
1
0
1
0
R
1
0
-
IVCE
R/W
PRTIM3
PRADC
0
0
R/W
R/W
0
0
0
0
Table 8-1
MCUCR
PRR1
PRR0
46