ATMEGA1284PR212-MU Atmel, ATMEGA1284PR212-MU Datasheet - Page 330

• Manufacturer Part Number: ATMEGA1284PR212-MU
• Description: BUNDLE ATMEGA1284P/RF212 QFN
• Manufacturer: Atmel

Specifications of ATMEGA1284PR212-MU

• Frequency: 2.4GHz
• Modulation Or Protocol: 802.15.4 Zigbee, 6LoWPAN, ISM
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Package / Case: 44-QFN, 32-QFN
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Development Tools By Supplier: ATAVRRZ541, ATAVRRAVEN, ATAVRRZUSBSTICK, ATAVRISP2, ATAVRRZ201
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Power - Output: -
• Operating Temperature: -
• Applications: -
• Sensitivity: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Details

Table 26-7.
Notes:
8059D–AVR–11/09
Symbol
t
t
t
t
t
t
HIGH
SU;STA
HD;DAT
SU;DAT
SU;STO
BUF
1. In ATmega1284P, this parameter is characterized and not 100% tested.
2. Required only for f
3. Cb = capacitance of one bus line in pF.
4. fCK = CPU clock frequency
5. This requirement applies to all ATmega1284P Two-wire Serial Interface operation. Other devices connected to the Two-wire
6. The actual low period generated by the ATmega1284P Two-wire Serial Interface is (1/f
7. The actual low period generated by the Two-wire Serial Interface is (1/f
Serial Bus need only obey the general f
than 6 MHz for the low time requirement to be strictly met at f
strictly met for f
speed (400 kHz) with other ATmega1284P devices, as well as any other device with a proper t
Parameter
High period of the SCL clock
Set-up time for a repeated START condition
Data hold time
Data setup time
Setup time for STOP condition
Bus free time between a STOP and START
condition
2-wire Serial Bus Requirements (Continued)
SCL
Figure 26-5. 2-wire Serial Bus Timing
SCL
> 308 kHz when f
> 100 kHz.
SCL
SDA
t
SU;STA
CK
= 8 MHz. Still, ATmega1284P devices connected to the bus may communicate at full
SCL
requirement.
t
HD;STA
t
t
of
LOW
f
f
f
f
f
f
f
f
f
f
f
f
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
Condition
t
HIGH
≤ 100 kHz
> 100 kHz
≤ 100 kHz
> 100 kHz
≤ 100 kHz
> 100 kHz
≤ 100 kHz
> 100 kHz
≤ 100 kHz
> 100 kHz
≤ 100 kHz
> 100 kHz
SCL
t
HD;DAT
= 100 kHz.
SCL
t
LOW
- 2/f
CK
t
SU;DAT
), thus the low time requirement will not be
SCL
250
100
Min
4.0
0.6
4.7
0.6
4.0
0.6
4.7
1.3
0
0
- 2/f
ATmega1284P
CK
LOW
), thus f
acceptance margin.
t
SU;STO
CK
t
r
3.45
Max
0.9
–
–
–
–
–
–
–
–
–
–
must be greater
t
BUF
Units
µs
µs
µs
µs
µs
µs
ns
ns
µs
µs
µs
µs
330