ATMEGA1284PR212-MU Atmel, ATMEGA1284PR212-MU Datasheet - Page 20

• Manufacturer Part Number: ATMEGA1284PR212-MU
• Description: BUNDLE ATMEGA1284P/RF212 QFN
• Manufacturer: Atmel

Specifications of ATMEGA1284PR212-MU

• Frequency: 2.4GHz
• Modulation Or Protocol: 802.15.4 Zigbee, 6LoWPAN, ISM
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Package / Case: 44-QFN, 32-QFN
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Development Tools By Supplier: ATAVRRZ541, ATAVRRAVEN, ATAVRRZUSBSTICK, ATAVRISP2, ATAVRRZ201
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Power - Output: -
• Operating Temperature: -
• Applications: -
• Sensitivity: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Details

6.5
8059D–AVR–11/09
I/O Memory
The I/O space definition of the ATmega1284P is shown in
All ATmega1284P I/Os and peripherals are placed in the I/O space. All I/O locations may be
accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32
general purpose working registers and the I/O space. I/O Registers within the address range
0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the
value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the
instruction set section for more details. When using the I/O specific commands IN and OUT, the
I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using
LD and ST instructions, 0x20 must be added to these addresses. The ATmega1284P is a com-
plex microcontroller with more peripheral units than can be supported within the 64 location
reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 -
0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most
other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore
be used on registers containing such Status Flags. The CBI and SBI instructions work with reg-
isters 0x00 to 0x1F only.
The I/O and peripherals control registers are explained in later sections.
The ATmega1284P contains three General Purpose I/O Registers, see
on page
useful for storing global variables and Status Flags. General Purpose I/O Registers within the
address range 0x00 - 0x1F are directly bit-accessible using the SBI, CBI, SBIS, and SBIC
instructions.
21. These registers can be used for storing any information, and they are particularly
”Register Summary” on page
ATmega1284P
”Register Description”
360.
20