ATMEGA1284PR212-MU Atmel, ATMEGA1284PR212-MU Datasheet - Page 188

• Manufacturer Part Number: ATMEGA1284PR212-MU
• Description: BUNDLE ATMEGA1284P/RF212 QFN
• Manufacturer: Atmel

Specifications of ATMEGA1284PR212-MU

• Frequency: 2.4GHz
• Modulation Or Protocol: 802.15.4 Zigbee, 6LoWPAN, ISM
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Package / Case: 44-QFN, 32-QFN
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Development Tools By Supplier: ATAVRRZ541, ATAVRRAVEN, ATAVRRZUSBSTICK, ATAVRISP2, ATAVRRZ201
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Power - Output: -
• Operating Temperature: -
• Applications: -
• Sensitivity: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Details

17.10.1
8059D–AVR–11/09
Using MPCMn
the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. When the
frame type bit is zero the frame is a data frame.
The Multi-processor Communication mode enables several slave MCUs to receive data from a
master MCU. This is done by first decoding an address frame to find out which MCU has been
addressed. If a particular slave MCU has been addressed, it will receive the following data
frames as normal, while the other slave MCUs will ignore the received frames until another
address frame is received.
For an MCU to act as a master MCU, it can use a 9-bit character frame format (UCSZn = 7). The
ninth bit (TXB8n) must be set when an address frame (TXB8n = 1) or cleared when a data frame
(TXB = 0) is being transmitted. The slave MCUs must in this case be set to use a 9-bit character
frame format.
The following procedure should be used to exchange data in Multi-processor Communication
mode:
1. All Slave MCUs are in Multi-processor Communication mode (MPCMn in UCSRnA is
2. The Master MCU sends an address frame, and all slaves receive and read this frame. In
3. Each Slave MCU reads the UDRn Register and determines if it has been selected. If so,
4. The addressed MCU will receive all data frames until a new address frame is received.
5. When the last data frame is received by the addressed MCU, the addressed MCU sets
Using any of the 5- to 8-bit character frame formats is possible, but impractical since the
Receiver must change between using n and n+1 character frame formats. This makes full-
duplex operation difficult since the Transmitter and Receiver uses the same character size set-
ting. If 5- to 8-bit character frames are used, the Transmitter must be set to use two stop bit
(USBSn = 1) since the first stop bit is used for indicating the frame type.
Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCMn bit. The
MPCMn bit shares the same I/O location as the TXCn Flag and this might accidentally be
cleared when using SBI or CBI instructions.
set).
the Slave MCUs, the RXCn Flag in UCSRnA will be set as normal.
it clears the MPCMn bit in UCSRnA, otherwise it waits for the next address byte and
keeps the MPCMn setting.
The other Slave MCUs, which still have the MPCMn bit set, will ignore the data frames.
the MPCMn bit and waits for a new address frame from master. The process then
repeats from 2.
ATmega1284P
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