ATMEGA1284PR212-MU Atmel, ATMEGA1284PR212-MU Datasheet - Page 153

• Manufacturer Part Number: ATMEGA1284PR212-MU
• Description: BUNDLE ATMEGA1284P/RF212 QFN
• Manufacturer: Atmel

Specifications of ATMEGA1284PR212-MU

• Frequency: 2.4GHz
• Modulation Or Protocol: 802.15.4 Zigbee, 6LoWPAN, ISM
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Package / Case: 44-QFN, 32-QFN
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Development Tools By Supplier: ATAVRRZ541, ATAVRRAVEN, ATAVRRZUSBSTICK, ATAVRISP2, ATAVRRZ201
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Power - Output: -
• Operating Temperature: -
• Applications: -
• Sensitivity: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Details

15.10 Timer/Counter Prescaler
15.11 Register Description
15.11.1
8059D–AVR–11/09
TCCR2A – Timer/Counter Control Register A
Figure 15-12. Prescaler for Timer/Counter2
The clock source for Timer/Counter2 is named clk
system I/O clock clk
clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter
(RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port C. A crystal can
then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock
source for Timer/Counter2. The Oscillator is optimized for use with a 32.768 kHz crystal. By set-
ting the EXCLK bit in the ASSR a 32 kHz external clock can be applied. See
Asynchronous Status Register” on page 158
For Timer/Counter2, the possible prescaled selections are: clk
clk
Setting the PSRASY bit in GTCCR resets the prescaler. This allows the user to operate with a
predictable prescaler.
• Bits 7:6 – COM2A1:0: Compare Match Output A Mode
These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0
bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2A pin
must be set in order to enable the output driver.
Bit
(0xB0)
Read/Write
Initial Value
T2S
/128, clk
PSRASY
TOSC1
clk
CS20
CS21
CS22
AS2
I/O
COM2A1
T2S
R/W
7
0
/256, and clk
IO
COM2A0
. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously
R/W
6
0
clk
T2S
T2S
COM2B1
/1024. Additionally, clk
R/W
5
0
Clear
COM2B0
R/W
4
0
for details.
TIMER/COUNTER2 CLOCK SOURCE
T2S
0
. clk
R
3
–
0
10-BIT T/C PRESCALER
T2S
T2S
clk
as well as 0 (stop) may be selected.
T2
is by default connected to the main
R
2
–
0
T2S
ATmega1284P
WGM21
R/W
/8, clk
1
0
T2S
WGM20
R/W
0
0
/32, clk
”ASSR –
TCCR2A
T2S
/64,
153