ATMEGA1284PR212-MU Atmel, ATMEGA1284PR212-MU Datasheet - Page 140

• Manufacturer Part Number: ATMEGA1284PR212-MU
• Description: BUNDLE ATMEGA1284P/RF212 QFN
• Manufacturer: Atmel

Specifications of ATMEGA1284PR212-MU

• Frequency: 2.4GHz
• Modulation Or Protocol: 802.15.4 Zigbee, 6LoWPAN, ISM
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Package / Case: 44-QFN, 32-QFN
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Development Tools By Supplier: ATAVRRZ541, ATAVRRAVEN, ATAVRRZUSBSTICK, ATAVRISP2, ATAVRRZ201
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Power - Output: -
• Operating Temperature: -
• Applications: -
• Sensitivity: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Details

15. 8-bit Timer/Counter2 with PWM and Asynchronous Operation
15.1
15.2
8059D–AVR–11/09
Features
Overview
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Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module.
A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 14-12.. For the actual
placement of I/O pins, see
ing I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations
are listed in the
The Power Reduction Timer/Counter2 bit, PRTIM2, in
page 46
Figure 15-1. 8-bit Timer/Counter Block Diagram
Single Channel Counter
Clear Timer on Compare Match (Auto Reload)
Glitch-free, Phase Correct Pulse Width Modulator (PWM)
Frequency Generator
10-bit Clock Prescaler
Overflow and Compare Match Interrupt Sources (TOV2, OCF2A and OCF2B)
Allows Clocking from External 32 kHz Watch Crystal Independent of the I/O Clock
must be written to zero to enable Timer/Counter2 module.
Status flags
”Register Description” on page
Timer/Counter
TCCRnA
OCRnA
TCNTn
OCRnB
=
=
”Pin Configurations” on page
Direction
Count
ASSRn
Clear
Synchronized Status flags
Control Logic
TOP
=
TCCRnB
asynchronous mode
Value
BOTTOM
Fixed
TOP
select (ASn)
clk
=
Tn
0
153.
Prescaler
Synchronization Unit
”PRR0 – Power Reduction Register 0” on
OCnA
(Int.Req.)
OCnB
(Int.Req.)
Generation
Generation
2. CPU accessible I/O Registers, includ-
Waveform
Waveform
ATmega1284P
TOVn
(Int.Req.)
OCnA
OCnB
Oscillator
T/C
clk
I/O
clk
clk
I/O
ASY
TOSC1
TOSC2
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