ATMEGA1284PR212-MU Atmel, ATMEGA1284PR212-MU Datasheet - Page 130

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ATMEGA1284PR212-MU

Manufacturer Part Number
ATMEGA1284PR212-MU
Description
BUNDLE ATMEGA1284P/RF212 QFN
Manufacturer
Atmel
Datasheet

Specifications of ATMEGA1284PR212-MU

Frequency
2.4GHz
Modulation Or Protocol
802.15.4 Zigbee, 6LoWPAN, ISM
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 4kB EEPROM, 16kB RAM
Antenna Connector
PCB, Surface Mount
Package / Case
44-QFN, 32-QFN
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
16 KB
Development Tools By Supplier
ATAVRRZ541, ATAVRRAVEN, ATAVRRZUSBSTICK, ATAVRISP2, ATAVRRZ201
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Supply
-
Power - Output
-
Operating Temperature
-
Applications
-
Sensitivity
-
Data Rate - Maximum
-
Current - Transmitting
-
Current - Receiving
-
Lead Free Status / Rohs Status
 Details
8059D–AVR–11/09
Figure 14-11. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (f
Figure 14-12
frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams
will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on.
The same renaming applies for modes that set the TOVn Flag at BOTTOM.
Figure 14-12. Timer/Counter Timing Diagram, no Prescaling
Figure 14-13
(PC and PFC PWM)
and ICFn
(CTC and FPWM)
OCRnx
TCNTn
OCFnx
TOVn
(Update at TOP)
(clk
clk
clk
OCRnx
I/O
TCNTn
TCNTn
as TOP)
(clk
I/O
Tn
clk
clk
/8)
I/O
(FPWM)
shows the count sequence close to TOP in various modes. When using phase and
shows the same timing data, but with the prescaler enabled.
I/O
Tn
/1)
(if used
OCRnx - 1
TOP - 1
TOP - 1
Old OCRnx Value
OCRnx
OCRnx Value
TOP
TOP
OCRnx + 1
BOTTOM
TOP - 1
New OCRnx Value
ATmega1284P
OCRnx + 2
BOTTOM + 1
TOP - 2
clk_I/O
/8)
130

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