ATMEGA1284PR212-MU Atmel, ATMEGA1284PR212-MU Datasheet - Page 13

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ATMEGA1284PR212-MU

Manufacturer Part Number
ATMEGA1284PR212-MU
Description
BUNDLE ATMEGA1284P/RF212 QFN
Manufacturer
Atmel
Datasheet

Specifications of ATMEGA1284PR212-MU

Frequency
2.4GHz
Modulation Or Protocol
802.15.4 Zigbee, 6LoWPAN, ISM
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 4kB EEPROM, 16kB RAM
Antenna Connector
PCB, Surface Mount
Package / Case
44-QFN, 32-QFN
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
16 KB
Development Tools By Supplier
ATAVRRZ541, ATAVRRAVEN, ATAVRRZUSBSTICK, ATAVRISP2, ATAVRRZ201
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Supply
-
Power - Output
-
Operating Temperature
-
Applications
-
Sensitivity
-
Data Rate - Maximum
-
Current - Transmitting
-
Current - Receiving
-
Lead Free Status / Rohs Status
 Details
5.7
8059D–AVR–11/09
Reset and Interrupt Handling
Figure 5-5.
Figure 5-6
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
Figure 5-6.
The AVR provides several different interrupt sources. These interrupts and the separate Reset
Vector each have a separate program vector in the program memory space. All interrupts are
assigned individual enable bits which must be written logic one together with the Global Interrupt
Enable bit in the Status Register in order to enable the interrupt. Depending on the Program
Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12
are programmed. This feature improves software security. See the section
ming” on page 291
The lowest addresses in the program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in
determines the priority levels of the different interrupts. The lower the address the higher is the
priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request
0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL
bit in the MCU Control Register (MCUCR). Refer to
The Reset Vector can also be moved to the start of the Boot Flash section by programming the
BOOTRST Fuse, see
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis-
abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled
Register Operands Fetch
2nd Instruction Execute
3rd Instruction Execute
1st Instruction Execute
ALU Operation Execute
2nd Instruction Fetch
3rd Instruction Fetch
4th Instruction Fetch
1st Instruction Fetch
Total Execution Time
shows the internal timing concept for the Register File. In a single clock cycle an ALU
Result Write Back
The Parallel Instruction Fetches and Instruction Executions
Single Cycle ALU Operation
for details.
clk
clk
”Memory Programming” on page
CPU
CPU
T1
T1
”Interrupts” on page 59
T2
T2
291.
”Interrupts” on page
T3
ATmega1284P
T3
for more information.
”Memory Program-
59. The list also
T4
T4
13

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