ATMEGA1284PR212-MU Atmel, ATMEGA1284PR212-MU Datasheet - Page 12

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ATMEGA1284PR212-MU

Manufacturer Part Number
ATMEGA1284PR212-MU
Description
BUNDLE ATMEGA1284P/RF212 QFN
Manufacturer
Atmel
Datasheet

Specifications of ATMEGA1284PR212-MU

Frequency
2.4GHz
Modulation Or Protocol
802.15.4 Zigbee, 6LoWPAN, ISM
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 4kB EEPROM, 16kB RAM
Antenna Connector
PCB, Surface Mount
Package / Case
44-QFN, 32-QFN
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
16 KB
Development Tools By Supplier
ATAVRRZ541, ATAVRRAVEN, ATAVRRZUSBSTICK, ATAVRISP2, ATAVRRZ201
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Supply
-
Power - Output
-
Operating Temperature
-
Applications
-
Sensitivity
-
Data Rate - Maximum
-
Current - Transmitting
-
Current - Receiving
-
Lead Free Status / Rohs Status
 Details
5.5.1
5.5.2
5.6
8059D–AVR–11/09
Instruction Execution Timing
SPH and SPL – Stack Pointer High and Stack pointer Low
RAMPZ – Extended Z-pointer Register for ELPM/SPM
For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as shown
in Figure 5-4. Note that LPM is not affected by the RAMPZ setting.
Figure 5-4.
The actual number of bits is implementation dependent. Unused bits in an implementation will
always read as zero. For compatibility with future devices, be sure to write these bits to zero.
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
chip. No internal clock division is used.
Figure 5-5 on page 13
by the Harvard architecture and the fast-access Register File concept. This is the basic pipelin-
ing concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions
per cost, functions per clocks, and functions per power-unit.
Bit
0x3E (0x5E)
0x3D (0x5D)
Read/Write
Initial Value
Bit
0x3B (0x5B)
Read/Write
Initial Value
Bit (
Individually)
Bit (Z-pointer)
The Z-pointer used by ELPM and SPM
RAMPZ7
R/W
R/W
SP7
15
7
0
R
7
0
1
23
7
shows the parallel instruction fetches and instruction executions enabled
RAMPZ6
R/W
SP6
R/W
RAMPZ
14
6
0
R
6
0
1
RAMPZ5
R/W
SP5
R/W
CPU
5
0
13
R
5
0
1
16
0
, directly generated from the selected clock source for the
RAMPZ4
R/W
SP12
SP4
R/W
R/W
4
0
12
4
1
1
15
7
RAMPZ3
R/W
SP11
SP3
R/W
R/W
3
0
11
3
0
1
ZH
RAMPZ2
R/W
SP10
2
0
SP2
R/W
R/W
10
2
0
1
0
8
ATmega1284P
RAMPZ1
R/W
SP9
SP1
R/W
R/W
1
0
9
1
0
1
7
7
RAMPZ0
R/W
SP8
SP0
R/W
R/W
0
0
8
0
0
1
ZL
RAMPZ
SPH
SPL
0
0
12

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