ATMEGA1284PR231-AU Atmel, ATMEGA1284PR231-AU Datasheet - Page 89

BUNDLE ATMEGA1284P/RF231 TQFP

ATMEGA1284PR231-AU

Manufacturer Part Number
ATMEGA1284PR231-AU
Description
BUNDLE ATMEGA1284P/RF231 TQFP
Manufacturer
Atmel
Datasheet

Specifications of ATMEGA1284PR231-AU

Frequency
2.4GHz
Modulation Or Protocol
802.15.4 Zigbee, 6LoWPAN, RF4CE, SP100, WirelessHART™, ISM
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 4kB EEPROM, 16kB RAM
Antenna Connector
PCB, Surface Mount
Package / Case
44-TQFP, 44-VQFP
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
16 KB
Development Tools By Supplier
ATAVRRZ541, ATAVRRAVEN, ATAVRRZUSBSTICK, ATAVRISP2, ATAVRRZ201
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Supply
-
Power - Output
-
Operating Temperature
-
Applications
-
Sensitivity
-
Data Rate - Maximum
-
Current - Transmitting
-
Current - Receiving
-
Lead Free Status / Rohs Status
 Details
8059D–AVR–11/09
Table 12-14. Overriding Signals for Alternate Functions in PD3:PD0
Note:
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
1. When enabled, the 2-wire Serial Interface enables Slew-Rate controls on the output pins PD0
and PD1. This is not shown in this table. In addition, spike filters are connected between the
AIO outputs shown in the port figure and the digital logic of the TWI module.
PD3/INT1/TXD1/
PCINT27
0
0
0
0
0
0
INT1 ENABLE
PCINT27 • PCIE3
1
INT1 INPUT
PCINT27 INPUT
PD2/INT0/RXD1/
PCINT26
PORTD2 • PUD
RXEN1
0
0
0
INT2 ENABLE
PCINT26 • PCIE3
1
INT0 INPUT
PCINT27 INPUT
PD1/TXD0/
PCINT25
TXEN
PORTD1 • PUD
TXEN
SDA_OUT
TWEN
0
INT1 ENABLE
PCINT25 • PCIE3
1
TXD
PCINT25 INPUT
ATmega1284P
(1)
PD0/RXD0/
PCINT27/T3
RXEN
PORTD0 • PUD
RXEN
SCL_OUT
TWEN
0
INT0 ENABLE
PCINT24 • PCIE3
1
RXD
PCINT24 INPUT
T3 INPUT
89

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