ATMEGA1284PR231-AU Atmel, ATMEGA1284PR231-AU Datasheet - Page 377

• Manufacturer Part Number: ATMEGA1284PR231-AU
• Description: BUNDLE ATMEGA1284P/RF231 TQFP
• Manufacturer: Atmel

Specifications of ATMEGA1284PR231-AU

• Frequency: 2.4GHz
• Modulation Or Protocol: 802.15.4 Zigbee, 6LoWPAN, RF4CE, SP100, WirelessHART™, ISM
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Development Tools By Supplier: ATAVRRZ541, ATAVRRAVEN, ATAVRRZUSBSTICK, ATAVRISP2, ATAVRRZ201
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Power - Output: -
• Operating Temperature: -
• Applications: -
• Sensitivity: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Details

8059D–AVR–11/09
21 ADC - Analog-to-digital Converter ..................................................... 240
22 JTAG Interface and On-chip Debug System ..................................... 260
23 IEEE 1149.1 (JTAG) Boundary-scan ................................................... 266
24 Boot Loader Support – Read-While-Write Self-Programming ......... 276
20.1Overview .............................................................................................................237
20.2Analog Comparator Multiplexed Input .................................................................237
20.3Register Description ............................................................................................238
21.1Features ..............................................................................................................240
21.2Overview .............................................................................................................240
21.3Operation .............................................................................................................241
21.4Starting a Conversion ..........................................................................................242
21.5Prescaling and Conversion Timing ......................................................................243
21.6Changing Channel or Reference Selection .........................................................246
21.7ADC Noise Canceler ...........................................................................................248
21.8ADC Conversion Result ......................................................................................253
21.9Register Description ............................................................................................255
22.1Features ..............................................................................................................260
22.2Overview .............................................................................................................260
22.3TAP – Test Access Port ......................................................................................260
22.4TAP Controller .....................................................................................................262
22.5Using the Boundary-scan Chain ..........................................................................263
22.6Using the On-chip Debug System .......................................................................263
22.7On-chip Debug Specific JTAG Instructions .........................................................264
22.8Using the JTAG Programming Capabilities .........................................................264
22.9Bibliography .........................................................................................................265
22.10Register Description ..........................................................................................265
23.1Features ..............................................................................................................266
23.2Overview .............................................................................................................266
23.3Data Registers .....................................................................................................267
23.4Boundary-scan Specific JTAG Instructions .........................................................268
23.5Boundary-scan Chain ..........................................................................................269
23.6ATmega1284P Boundary-scan Order .................................................................272
23.7Boundary-scan Description Language Files ........................................................274
23.8Register Description ............................................................................................275
24.1Features ..............................................................................................................276
ATmega1284P
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