ATMEGA1284PR231-AU Atmel, ATMEGA1284PR231-AU Datasheet - Page 293

• Manufacturer Part Number: ATMEGA1284PR231-AU
• Description: BUNDLE ATMEGA1284P/RF231 TQFP
• Manufacturer: Atmel

Specifications of ATMEGA1284PR231-AU

• Frequency: 2.4GHz
• Modulation Or Protocol: 802.15.4 Zigbee, 6LoWPAN, RF4CE, SP100, WirelessHART™, ISM
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Development Tools By Supplier: ATAVRRZ541, ATAVRRAVEN, ATAVRRZUSBSTICK, ATAVRISP2, ATAVRRZ201
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Power - Output: -
• Operating Temperature: -
• Applications: -
• Sensitivity: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Details

8059D–AVR–11/09
Table 25-4.
Note:
Table 25-5.
Note:
The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if
Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the Lock bits.
Fuse High Byte
OCDEN
JTAGEN
SPIEN
WDTON
EESAVE
BOOTSZ1
BOOTSZ0
BOOTRST
Fuse Low Byte
CKDIV8
CKOUT
SUT1
SUT0
CKSEL3
CKSEL2
CKSEL1
CKSEL0
(1)
1. The SPIEN Fuse is not accessible in serial programming mode.
2. The default value of BOOTSZ1..0 results in maximum Boot Size. See
3. See
4. Never ship a product with the OCDEN Fuse programmed regardless of the setting of Lock bits
1. The default value of SUT1..0 results in maximum start-up time for the default clock source.
2. The default setting of CKSEL3..0 results in internal RC Oscillator @ 8 MHz. See
3. The CKOUT Fuse allow the system clock to be output on PORTB1. See
4. See
(3)
(4)
(4)
(3)
for details.
and JTAGEN Fuse. A programmed OCDEN Fuse enables some parts of the clock system to
be running in all sleep modes. This may increase the power consumption.
See
page 28
on page 36
Fuse High Byte
Fuse Low Byte
”WDTCSR – Watchdog Timer Control Register” on page 57
”System and Reset Characteristics” on page 327
”System Clock Prescaler” on page 36
for details.
Bit No
for details.
7
6
5
4
3
2
1
0
Bit No
7
6
5
4
3
2
0
1
Description
Enable OCD
Enable JTAG
Enable Serial Program and Data
Downloading
Watchdog Timer always on
EEPROM memory is preserved
through the Chip Erase
Select Boot Size (see
details)
Select Boot Size (see
details)
Select Reset Vector
Description
Divide clock by 8
Clock output
Select start-up time
Select start-up time
Select Clock source
Select Clock source
Select Clock source
Select Clock source
for details.
Table 25-9
Table 25-9
for details.
for
for
Default Value
1 (unprogrammed, OCD
disabled)
0 (programmed, JTAG enabled)
0 (programmed, SPI prog.
enabled)
1 (unprogrammed)
1 (unprogrammed, EEPROM
not preserved)
0 (programmed)
0 (programmed)
1 (unprogrammed)
Default Value
0 (programmed)
1 (unprogrammed)
1 (unprogrammed)
0 (programmed)
0 (programmed)
0 (programmed)
1 (unprogrammed)
0 (programmed)
ATmega1284P
for details.
Table 24-7 on page 288
”Clock Output Buffer”
(2)
(2)
(1)
(2)
(2)
(2)
Table 7-1 on
(1)
(2)
293