ATMEGA1284PR231-AU Atmel, ATMEGA1284PR231-AU Datasheet - Page 235

• Manufacturer Part Number: ATMEGA1284PR231-AU
• Description: BUNDLE ATMEGA1284P/RF231 TQFP
• Manufacturer: Atmel

Specifications of ATMEGA1284PR231-AU

• Frequency: 2.4GHz
• Modulation Or Protocol: 802.15.4 Zigbee, 6LoWPAN, RF4CE, SP100, WirelessHART™, ISM
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Development Tools By Supplier: ATAVRRZ541, ATAVRRAVEN, ATAVRRZUSBSTICK, ATAVRISP2, ATAVRRZ201
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Power - Output: -
• Operating Temperature: -
• Applications: -
• Sensitivity: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Details

19.9.5
19.9.6
8059D–AVR–11/09
TWAR – TWI (Slave) Address Register
TWAMR – TWI (Slave) Address Mask Register
of a lost bus arbitration, no data is lost in the transition from Master to Slave. Handling of the
ACK bit is controlled automatically by the TWI logic, the CPU cannot access the ACK bit directly.
• Bits 7:0 – TWD: TWI Data Register
These eight bits constitute the next data byte to be transmitted, or the latest data byte received
on the 2-wire Serial Bus.
The TWAR should be loaded with the 7-bit Slave address (in the seven most significant bits of
TWAR) to which the TWI will respond when programmed as a Slave Transmitter or Receiver,
and not needed in the Master modes. In multimaster systems, TWAR must be set in masters
which can be addressed as Slaves by other Masters.
The LSB of TWAR is used to enable recognition of the general call address (0x00). There is an
associated address comparator that looks for the slave address (or general call address if
enabled) in the received serial address. If a match is found, an interrupt request is generated.
• Bits 7:1 – TWA: TWI (Slave) Address Register
These seven bits constitute the slave address of the TWI unit.
• Bit 0 – TWGCE: TWI General Call Recognition Enable Bit
If set, this bit enables the recognition of a General Call given over the 2-wire Serial Bus.
• Bits 7:1 – TWAM: TWI Address Mask
The TWAMR can be loaded with a 7-bit Slave Address mask. Each of the bits in TWAMR can
mask (disable) the corresponding address bit in the TWI Address Register (TWAR). If the mask
bit is set to one then the address match logic ignores the compare between the incoming
address bit and the corresponding bit in TWAR.
detail.
Bit
(0xBA)
Read/Write
Initial Value
Bit
(0xBD)
Read/Write
Initial Value
TWA6
R/W
R/W
7
1
7
0
TWA5
R/W
R/W
6
1
6
0
TWA4
R/W
R/W
5
1
5
0
TWAM[6:0]
TWA3
R/W
R/W
4
1
4
0
Figure 19-22
TWA2
R/W
R/W
3
1
3
0
TWA1
R/W
R/W
shows the address match logic in
2
1
2
0
ATmega1284P
TWA0
R/W
R/W
1
1
1
0
TWGCE
R/W
R
0
0
0
–
0
TWAMR
TWAR
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