ATMEGA1284PR231-AU Atmel, ATMEGA1284PR231-AU Datasheet - Page 213
ATMEGA1284PR231-AU
Manufacturer Part Number
ATMEGA1284PR231-AU
Description
BUNDLE ATMEGA1284P/RF231 TQFP
Manufacturer
Atmel
Datasheet
1.ATMEGA1284PR231-AU.pdf
(380 pages)
Specifications of ATMEGA1284PR231-AU
Frequency
2.4GHz
Modulation Or Protocol
802.15.4 Zigbee, 6LoWPAN, RF4CE, SP100, WirelessHART™, ISM
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 4kB EEPROM, 16kB RAM
Antenna Connector
PCB, Surface Mount
Package / Case
44-TQFP, 44-VQFP
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
16 KB
Development Tools By Supplier
ATAVRRZ541, ATAVRRAVEN, ATAVRRZUSBSTICK, ATAVRISP2, ATAVRRZ201
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Supply
-
Power - Output
-
Operating Temperature
-
Applications
-
Sensitivity
-
Data Rate - Maximum
-
Current - Transmitting
-
Current - Receiving
-
Lead Free Status / Rohs Status
Details
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19.5
19.5.1
19.5.2
8059D–AVR–11/09
Overview of the TWI Module
SCL and SDA Pins
Bit Rate Generator Unit
The TWI module is comprised of several submodules, as shown in
drawn in a thick line are accessible through the AVR data bus.
Figure 19-9. Overview of the TWI Module
These pins interface the AVR TWI with the rest of the MCU system. The output drivers contain a
slew-rate limiter in order to conform to the TWI specification. The input stages contain a spike
suppression unit removing spikes shorter than 50 ns. Note that the internal pull-ups in the AVR
pads can be enabled by setting the PORT bits corresponding to the SCL and SDA pins, as
explained in the I/O Port section. The internal pull-ups can in some systems eliminate the need
for external ones.
This unit controls the period of SCL when operating in a Master mode. The SCL period is con-
trolled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in the TWI Status
Register (TWSR). Slave operation does not depend on Bit Rate or Prescaler settings, but the
CPU clock frequency in the Slave must be at least 16 times higher than the SCL frequency. Note
that slaves may prolong the SCL low period, thereby reducing the average TWI bus clock
period. The SCL frequency is generated according to the following equation:
Slew-rate
Address Match Unit
Arbitration detection
Control
START / STOP
Address Comparator
Address Register
Control
SCL
(TWAR)
Spike
Filter
Bus Interface Unit
Address/Data Shift
Spike Suppression
Register (TWDR)
Slew-rate
Control
SDA
Status Register
Ack
Spike
Filter
(TWSR)
State Machine and
Control Unit
Status control
Bit Rate Generator
ATmega1284P
Control Register
Bit Rate Register
Figure
Prescaler
(TWCR)
(TWBR)
19-9. All registers
213
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