ATMEGA1284PR231-AU Atmel, ATMEGA1284PR231-AU Datasheet - Page 168

• Manufacturer Part Number: ATMEGA1284PR231-AU
• Description: BUNDLE ATMEGA1284P/RF231 TQFP
• Manufacturer: Atmel

Specifications of ATMEGA1284PR231-AU

• Frequency: 2.4GHz
• Modulation Or Protocol: 802.15.4 Zigbee, 6LoWPAN, RF4CE, SP100, WirelessHART™, ISM
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Development Tools By Supplier: ATAVRRZ541, ATAVRRAVEN, ATAVRRZUSBSTICK, ATAVRISP2, ATAVRRZ201
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Power - Output: -
• Operating Temperature: -
• Applications: -
• Sensitivity: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Details

16.5
16.5.1
8059D–AVR–11/09
Register Description
SPCR – SPI Control Register
• Bit 7 – SPIE: SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if
the Global Interrupt Enable bit in SREG is set.
• Bit 6 – SPE: SPI Enable
When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI
operations.
• Bit 5 – DORD: Data Order
When the DORD bit is written to one, the LSB of the data word is transmitted first.
When the DORD bit is written to zero, the MSB of the data word is transmitted first.
• Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic
zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared,
and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Mas-
ter mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low
when idle. Refer to
marized below:
Table 16-3.
• Bit 2 – CPHA: Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or
trailing (last) edge of SCK. Refer to
functionality is summarized below:
Table 16-4.
Bit
0x2C (0x4C)
Read/Write
Initial Value
CPOL
CPHA
CPOL Functionality
CPHA Functionality
0
1
0
1
SPIE
R/W
7
0
Figure 16-3
SPE
R/W
6
0
and
DORD
R/W
5
0
Figure 16-4
Figure 16-3
Leading Edge
Leading Edge
MSTR
Sample
Falling
R/W
Rising
Setup
4
0
for an example. The CPOL functionality is sum-
and
CPOL
R/W
3
0
Figure 16-4
CPHA
R/W
2
0
for an example. The CPOL
ATmega1284P
SPR1
R/W
1
0
Trailing Edge
Trailing Edge
Sample
Falling
Rising
Setup
SPR0
R/W
0
0
SPCR
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