ATMEGA1284PR231-AU Atmel, ATMEGA1284PR231-AU Datasheet - Page 157

• Manufacturer Part Number: ATMEGA1284PR231-AU
• Description: BUNDLE ATMEGA1284P/RF231 TQFP
• Manufacturer: Atmel

Specifications of ATMEGA1284PR231-AU

• Frequency: 2.4GHz
• Modulation Or Protocol: 802.15.4 Zigbee, 6LoWPAN, RF4CE, SP100, WirelessHART™, ISM
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Development Tools By Supplier: ATAVRRZ541, ATAVRRAVEN, ATAVRRZUSBSTICK, ATAVRISP2, ATAVRRZ201
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Power - Output: -
• Operating Temperature: -
• Applications: -
• Sensitivity: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Details

15.11.3
8059D–AVR–11/09
TCNT2 – Timer/Counter Register
• Bit 6 – FOC2B: Force Output Compare B
The FOC2B bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when
TCCR2B is written when operating in PWM mode. When writing a logical one to the FOC2B bit,
an immediate Compare Match is forced on the Waveform Generation unit. The OC2B output is
changed according to its COM2B1:0 bits setting. Note that the FOC2B bit is implemented as a
strobe. Therefore it is the value present in the COM2B1:0 bits that determines the effect of the
forced compare.
A FOC2B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR2B as TOP.
The FOC2B bit is always read as zero.
• Bits 5:4 – Res: Reserved Bits
These bits are reserved bits in the ATmega1284P and will always read as zero.
• Bit 3 – WGM22: Waveform Generation Mode
See the description in the
• Bit 2:0 – CS22:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter, see
15-9 on page
Table 15-9.
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes) the Compare
Bit
(0xB2)
Read/Write
Initial Value
CS22
0
0
0
0
1
1
1
1
157.
Clock Select Bit Description
R/W
7
0
CS21
0
0
1
1
0
0
1
1
R/W
”TCCR2A – Timer/Counter Control Register A” on page
6
0
CS20
R/W
0
1
0
1
0
1
0
1
5
0
R/W
Description
No clock source (Timer/Counter stopped).
clk
clk
clk
clk
clk
clk
clk
4
0
TCNT2[7:0]
T2S
T2S
T2S
T2S
T2S
T
T
2
2
S
S
/256 (From prescaler)
/1024 (From prescaler)
/(No prescaling)
/8 (From prescaler)
/32 (From prescaler)
/64 (From prescaler)
/128 (From prescaler)
R/W
3
0
R/W
2
0
ATmega1284P
R/W
1
0
R/W
0
0
153.
TCNT2
Table
157