MC9328MX21SCVK Freescale Semiconductor, MC9328MX21SCVK Datasheet - Page 92

• Manufacturer Part Number: MC9328MX21SCVK
• Description: IC MCU I.MX21 266MHZ 289-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX21r

Specifications of MC9328MX21SCVK

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: 1-Wire, EBI/EMI, I²C, IrDA, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 192
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 1.45 V ~ 3.3 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-MAPBGA
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Specifications
3.21
The I
Direction, Slave Acknowledge, Data, Data Acknowledge, and STOP.
3.22
The CSI module consists of a control register to configure the interface timing, a control register for
statistic data generation, a status register, interface logic, a 32 × 32 image data receive FIFO, and a 16 × 32
statistic data FIFO.
3.22.1
Figure 81
and the CSI is programmed to received data on the positive edge.
when the CMOS sensor output data is configured for positive edge and the CSI is programmed to received
data in negative edge. The parameters for the timing diagrams are listed in
calculating the pixel clock rise and fall time is located in
Fall
92
Time.”
2
Ref
No.
C communication protocol consists of seven elements: START, Data Source/Recipient, Data
1
2
3
4
5
6
I
CMOS Sensor Interface
shows the timing diagram when the CMOS sensor output data is configured for negative edge
2
Gated Clock Mode
SCL Clock Frequency
Hold time (repeated) START condition
Data hold time
Data setup time
HIGH period of the SCL clock
LOW period of the SCL clock
Setup time for STOP condition
C Module
SDA
SCL
Parameter
Figure 80. Definition of Bus Timing for I
1
Table 44. I
5
MC9328MX21 Technical Data, Rev. 3.4
2
2
C Bus Timing Parameters
3
Minimum
114.8
336.4
110.5
69.7
3.1
0
0
1.8 V ± 0.1 V
Section 3.22.3, “Calculation of Pixel Clock Rise/
4
Maximum
69.7
100
–
–
–
–
–
Figure 82
2
C
Minimum
335.1
111.1
111.1
Table
1.76
68.3
shows the timing diagram
0
0
6
3.0 V ± 0.3 V
45. The formula for
Freescale Semiconductor
Maximum
72.3
100
–
–
–
–
–
Unit
kHz
ns
ns
ns
ns
ns
ns