MC9328MX21SCVK Freescale Semiconductor, MC9328MX21SCVK Datasheet - Page 56

• Manufacturer Part Number: MC9328MX21SCVK
• Description: IC MCU I.MX21 266MHZ 289-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX21r

Specifications of MC9328MX21SCVK

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: 1-Wire, EBI/EMI, I²C, IrDA, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 192
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 1.45 V ~ 3.3 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-MAPBGA
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

1. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non- inverted frame sync
Specifications
56
Ref
No.
11a
11b
27a
27b
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting
the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
28
29
30
31
32
33
34
(Tx) CK high to STXD high impedance
SRXD setup before (Tx) CK falling
SRXD setup before (Tx) CK falling
SRXD hold after (Tx) CK falling
(Tx) CK high to STXD high
(Tx) CK high to STXD low
SRXD setup time before (Rx) CK low
SRXD hold time after (Rx) CK low
(Tx/Rx) CK clock period
(Tx/Rx) CK clock high period
(Tx/Rx) CK clock low period
(Tx) CK high to FS (bl) high
(Rx) CK high to FS (bl) high
(Tx) CK high to FS (bl) low
(Rx) CK high to FS (bl) low
(Tx) CK high to FS (wl) high
(Rx) CK high to FS (wl) high
(Tx) CK high to FS (wl) low
(Rx) CK high to FS (wl) low
(Tx) CK high to STXD valid from high impedance
(Tx) CK high to STXD high
(Tx) CK high to STXD low
(Tx) CK high to STXD high impedance
SRXD setup time before (Rx) CK low
SRXD hole time after (Rx) CK low
SRXD hold after (Tx) CK falling
Table 36. SSI to SSI2 Ports Timing Parameters (Continued)
Parameter
1
90
Synchronous External Clock Operation (SSI2 Ports)
Synchronous Internal Clock Operation (SSI2 Ports)
MC9328MX21 Technical Data, Rev. 3.4
External Clock Operation (SSI2 Ports)
Minimum
21.50
36.36
36.36
10.40
10.40
10.40
10.40
20.78
11.00
11.00
11.00
11.00
0.34
0.34
9.59
9.59
9.59
2.52
4.42
0.34
9.59
0
0
0
0
.91
1.8 V ± 0.1 V
Maximum
17.37
19.70
17.37
19.70
17.37
19.70
17.37
19.70
17.08
17.08
17.08
16.84
0.72
0.72
0.48
–
–
–
–
–
–
–
–
–
–
–
Minimum
21.50
90.91
36.36
36.36
20.78
0.34
0.34
0.34
8.67
9.28
8.67
9.28
8.67
9.28
8.67
9.28
7.86
7.86
7.86
7.86
2.52
4.42
0
0
0
0
3.0 V ± 0.3 V
Freescale Semiconductor
Maximum
15.88
18.21
15.88
18.21
15.88
18.21
15.88
18.21
15.59
15.59
15.59
15.35
0.72
0.72
0.48
–
–
–
–
–
–
–
–
–
–
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns