X40021V14I-AT1 Intersil, X40021V14I-AT1 Datasheet - Page 12
![IC VOLTAGE MONITOR DUAL 14-TSSOP](/photos/6/58/65830/20-14-tssop_sml.jpg)
X40021V14I-AT1
Manufacturer Part Number
X40021V14I-AT1
Description
IC VOLTAGE MONITOR DUAL 14-TSSOP
Manufacturer
Intersil
Type
Multi-Voltage Supervisorr
Datasheet
1.X40020S14Z-A.pdf
(24 pages)
Specifications of X40021V14I-AT1
Number Of Voltages Monitored
2
Output
Open Drain or Open Collector
Reset
Active Low
Reset Timeout
Adjustable/Selectable
Voltage - Threshold
2.9V, 4.6V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
14-TSSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Figure 10. Byte Write Sequence
Stops and Write Modes
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte plus the subsequent ACK signal. If a stop is
issued in the middle of a data byte, or before 1 full
data byte plus its associated ACK is sent, then the
device will reset itself without performing the write. The
contents of the array will not be effected.
Acknowledge Polling
can be used to take advantage of the typical 5ms write
cycle time. Once the stop condition is issued to indi-
cate the end of the master’s byte load operation, the
device initiates the internal high voltage cycle.
Acknowledge polling can be initiated immediately. To
do this, the master issues a start condition followed by
the Slave Address Byte for a write or read operation. If
the device is still busy with the high voltage cycle then
no ACK will be returned. If the device has completed
the write operation, an ACK will be returned and the
host can then proceed with the read or write operation.
See Figure 11.
Serial Read Operations
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the Slave Address Byte is set to one.
The disabling of the inputs during high voltage cycles
Signals from
Signals from
the Master
the Slave
SDA Bus
12
S
a
t
r
t
Address
Slave
X40020, 40021
0
A
C
K
Address
Byte
Figure 11. Acknowledge Polling Sequence
C
A
K
Command Sequence?
Command Sequence
Issue Slave Address
Byte (Read or Write)
Byte Load Completed
Complete. Continue
High Voltage Cycle
Continue Normal
Enter ACK Polling
by Issuing STOP.
Read or Write
Issue START
PROCEED
Returned?
Data
ACK
YES
YES
A
C
K
S
o
p
t
NO
NO
Issue STOP
Issue STOP
May 17, 2006
FN8112.1