SE5230DR2G ON Semiconductor, SE5230DR2G Datasheet - Page 6

• Manufacturer Part Number: SE5230DR2G
• Description: IC OP AMP LOW VOLTAGE 8-SOIC
• Manufacturer: ON Semiconductor
• Type: General Purpose Amplifierr

Specifications of SE5230DR2G

• Amplifier Type: General Purpose
• Number Of Circuits: 1
• Output Type: Rail-to-Rail
• Slew Rate: 0.25 V/µs
• Gain Bandwidth Product: 600kHz
• Current - Input Bias: 40nA
• Voltage - Input Offset: 400µV
• Current - Supply: 1.1mA
• Current - Output / Channel: 32mA
• Voltage - Supply, Single/dual (±): 1.8 V ~ 15 V, ±0.9 V ~ 7.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Number Of Channels: 1
• Voltage Gain Db: 126.02 dB
• Common Mode Rejection Ratio (min): 85 dB
• Input Offset Voltage: 3 mV
• Operating Supply Voltage: 3 V, 5 V, 9 V, 12 V
• Supply Current: 1.6 mA
• Maximum Power Dissipation: 500 mW
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Maximum Dual Supply Voltage: +/- 7.5 V
• Minimum Operating Temperature: - 40 C
• Rail/rail I/o Type: No
• Number Of Elements: 1
• Unity Gain Bandwidth Product: 0.6MHz
• Common Mode Rejection Ratio: 85dB
• Input Bias Current: 150nA
• Single Supply Voltage (typ): 3/5/9/12V
• Dual Supply Voltage (typ): ±3/±5V
• Power Dissipation: 500mW
• Voltage Gain In Db: 126.02dB
• Power Supply Rejection Ratio: 85dB
• Power Supply Requirement: Single/Dual
• Shut Down Feature: No
• Single Supply Voltage (min): 1.8V
• Single Supply Voltage (max): 15V
• Dual Supply Voltage (min): ±0.9V
• Dual Supply Voltage (max): ±7.5V
• Technology: Bipolar
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 8
• Package Type: SOIC N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• -3db Bandwidth: -
• Lead Free Status / Rohs Status: Details

Input Stage
minimum supply voltages should have input and output
stage swings capable of reaching both supply voltages
within a few millivolts in order to achieve ease of quiescent
biasing and to have maximum input/output signal handling
capability. The input stage of the NE5230 has a
common−mode voltage range that not only includes the
entire supply voltage range, but also allows either supply to
be exceeded by 250 mV without increasing the input offset
voltage by more than 6.0 mV. This is unequalled by any
other operational amplifier today.
common−mode range, two emitter−coupled differential
pairs are placed in parallel so that the common−mode
voltage of one can reach the positive supply rail and the other
can reach the negative supply rail. The simplified schematic
of Figure 1 shows how the complementary emitter−coupler
transistors are configured to form the basic input stage cell.
Common−mode input signal voltages in the range from
0.8 V above V
pair, Q3 and Q4, while common−mode input signal voltages
in the range of V
by the PNP pair, Q1 and Q2. The intermediate range of input
voltages requires that both the NPN and PNP pairs are
operating. The collector currents of the input transistors are
summed by the current combiner circuit composed of
transistors Q8 through Q11 into one output current.
Transistor Q8 is connected as a diode to ensure that the
outputs of Q2 and Q4 are properly subtracted from those of
Q1 and Q3.
problems for rail−to−rail capability. As the common−mode
Operational amplifiers which are able to function at
In order to accomplish the feat of rail−to−rail input
The input stage was designed to overcome two important
EE
V
EE
to V
IN−
to 0.8 V above V
CC
are handled completely by the NPN
V
Q3
+
V
b1
Q1
EE
are processed only
Q6
Q5
THEORY OF OPERATION
I
b1
http://onsemi.com
Q7
Q2
Figure 1. Input Stage
Q4
6
voltage moves from the range where only the NPN pair was
operating to where both of the input pairs were operating, the
effective transconductance would change by a factor of two.
Frequency compensation for the ranges where one input pair
was operating would, of course, not be optimal for the range
where both pairs were operating. Secondly, fast changes in
the common−mode voltage would abruptly saturate and
restore the emitter current sources, causing transient
distortion. These problems were overcome by assuring that
only the input transistor pair which is able to function
properly is active. The NPN pair is normally activated by the
current source I
Q7, assuming the PNP pair is non−conducting. When the
common−mode input voltage passes below the reference
voltage, V
gradually steered toward the PNP pair, away from the NPN
pair. The transfer of the emitter currents between the
complementary input pairs occurs in a voltage range of
about 120 mV around the reference voltage V
the sum of the emitter currents for each of the NPN and PNP
transistor pairs is kept constant; this ensures that the
transconductance of the parallel combination will be
constant, since the transconductance of bipolar transistors is
proportional to their emitter currents.
minimize the changes in input offset voltage between that of
the NPN and PNP transistor pair which occurs when the
input common−mode voltage crosses the internal reference
voltage, V
quad for each input pair has yielded a typical input offset
voltage of less than 0.3 mV and a change in the input offset
voltage of less than 0.1 mV.
An essential requirement of this kind of input stage is to
V
IN+
B1
B1
. Careful circuit layout with a cross−coupled
− 0.8 V at the base of Q5, the emitter current is
B1
Q10
Q8
through Q5 and the current mirror Q6 and
R10
R8
Q11
Q9
R11
R9
V
+
V
b2
V
B1
I
V
OUT
CC
EE
. In this way