MC16Z3BCAG16 Freescale Semiconductor, MC16Z3BCAG16 Datasheet - Page 426

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MC16Z3BCAG16

Manufacturer Part Number
MC16Z3BCAG16
Description
IC MCU 16BIT HI SPEED 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HC16r
Datasheet

Specifications of MC16Z3BCAG16

Core Processor
CPU16
Core Size
16-Bit
Speed
16MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
Mask ROM
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC16Z3BCAG16
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
D.6.15 Transmit Data RAM
TR[0:F] — Transmit Data RAM
D.6.16 Command RAM
CR[0:F] — Command RAM
CONT — Continue
BITSE — Bits per Transfer Enable
D-52
Data that is to be transmitted by the QSPI is stored in this segment. The CPU16 nor-
mally writes one word of data into this segment for each queue command to be exe-
cuted. Information to be transmitted must be written to the transmit data RAM in a
right-justified format. The QSPI cannot modify information in the transmit data RAM.
The QSPI copies the information to its data serializer for transmission. Information re-
mains in the transmit RAM until overwritten.
Command RAM is used by the QSPI when in master mode. The CPU16 writes one
byte of control information to this segment for each QSPI command to be executed.
The QSPI cannot modify information in command RAM.
Command RAM consists of 16 bytes. Each byte is divided into two fields. The periph-
eral chip-select field enables peripherals for transfer. The command control field pro-
vides transfer options.
A maximum of 16 commands can be in the queue. Queue execution proceeds from
the address in NEWQP through the address in ENDQP (both of these fields are in
SPCR2).
0 = Control of chip selects returned to PORTQS after transfer is complete.
1 = Peripheral chip selects remain asserted after transfer is complete. This allows
0 = Eight bits
1 = Number of bits set in BITS field of SPCR0.
for transfers greater than 16 bits to peripherals without negation of their chip-
selects.
NOTES:
CONT
CONT
1. The PCS0 bit represents the dual-function PCS0/SS.
7
COMMAND CONTROL
BITSE
BITSE
Freescale Semiconductor, Inc.
6
For More Information On This Product,
DT
DT
5
Go to: www.freescale.com
REGISTER SUMMARY
DSCK
DSCK
4
PCS3
PCS3
3
PERIPHERAL CHIP SELECT
PCS2
PCS2
2
PCS1
PCS1
1
$YFFD20 – $YFFD3F
$YFFD40 – $YFFD4F
M68HC16 Z SERIES
PCS0
PCS0
0
USER’S MANUAL
1
1

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