DF2338VFC25IV Renesas Electronics America, DF2338VFC25IV Datasheet - Page 93
DF2338VFC25IV
Manufacturer Part Number
DF2338VFC25IV
Description
MCU 3V 256K I-TEMP PB-FREE 144-Q
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2338VFC25IV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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2.8.2
When the RES input goes low all current processing stops and the CPU enters the reset state. All
interrupts are masked in the reset state. Reset exception handling starts when the RES signal
changes from low to high.
The reset state can also be entered by a watchdog timer overflow. For details, refer to section 13,
Watchdog Timer.
Notes: 1.
RES = high
Exception-handling state
Reset State
2.
Bus-released state
From any state except hardware standby mode, a transition to the reset state occurs whenever RES
goes low. A transition can also be made to the reset state when the watchdog timer overflows.
From any state, a transition to hardware standby mode occurs when STBY goes low.
Reset state
End of bus
request
End of
exception
handling
*1
Figure 2.12 State Transitions
Bus
request
STBY = high, RES = low
External interrupt
Request for
exception
handling
Program execution
End of bus request
Bus request
state
Interrupt
request
SLEEP
instruction
with
SSBY = 1
Rev.4.00 Sep. 07, 2007 Page 61 of 1210
Hardware standby mode
SLEEP
instruction
with
SSBY = 0
Software standby mode
Power-down state
Sleep mode
REJ09B0245-0400
*2
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