DF2338VFC25IV Renesas Electronics America, DF2338VFC25IV Datasheet - Page 737
DF2338VFC25IV
Manufacturer Part Number
DF2338VFC25IV
Description
MCU 3V 256K I-TEMP PB-FREE 144-Q
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2338VFC25IV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Bit 5—A/D Start (ADST): Selects starting or stopping of A/D conversion. Holds a value of 1
during A/D conversion.
The ADST bit can be set to 1 by software, a timer conversion start trigger, or the A/D external
trigger input pin (ADTRG).
Bit 5
ADST
0
1
Bit 4—Scan Mode (SCAN): Selects single mode or scan mode as the A/D conversion operating
mode. See section 16.4, Operation, for details of single mode and scan mode operation. Only set
the SCAN bit while conversion is stopped (ADST = 0).
Bit 4
SCAN
0
1
Bit 3—Clock Select (CKS): Used together with the CKS1 bit in ADCR to set the A/D
conversion time. Only change the conversion time while conversion is stopped (ADST = 0).
ADCR Bit 3
CKS1
0
1
Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): These bits are used together with the CH3 bit
in ADCR and SCAN bit to select the analog input channels.
Only set the input channel(s) while conversion is stopped (ADST = 0).
Description
•
•
•
Description
Single mode
Scan mode
Bit 3
CKS
0
1
0
1
A/D conversion stopped
Single mode: A/D conversion is started. Cleared to 0 automatically when
Scan mode:
Description
Conversion time = 530 states (max.)
Conversion time = 68 states (max.)
Conversion time = 266 states (max.)
Conversion time = 134 states (max.)
conversion on the specified channel ends
A/D conversion is started. Conversion continues sequentially on the
selected channels until ADST is cleared to 0 by software, a reset, or
a transition to standby mode or module stop mode
Rev.4.00 Sep. 07, 2007 Page 705 of 1210
REJ09B0245-0400
(Initial value)
(Initial value)
(Initial value)
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