DF2315VTE25 Renesas Electronics America, DF2315VTE25 Datasheet - Page 784
DF2315VTE25
Manufacturer Part Number
DF2315VTE25
Description
MCU 3V 384K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2315VTE25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2315VTE25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 17 ROM
Table 17.58 Commands in PROM Mode
Command
Memory-read
mode
Auto-program
mode
Auto-erase
mode
Status-read
mode
17.28.3 Memory-Read Mode
(1) On completion of an automatic program, automatic erase, or status read, the LSI enters a
(2) In memory-read mode, the writing of commands is possible in the same way as in the
(3) After entering memory-read mode, continuous reading is possible.
(4) After power has first been supplied, the LSI enters the memory-read mode. For the AC
Rev.7.00 Feb. 14, 2007 page 750 of 1108
REJ09B0089-0700
Notes: 1. In auto-program mode, 129 cycles are required in command writing because of the
command waiting state. So, to read the contents of memory after these operations, issue the
command to change the mode to the memory-read mode before reading from the memory.
command-write state.
characteristics in memory read mode, see section 17.29.2, AC Characteristics and Timing in
PROM Mode.
2. In memory read mode, the number of cycles varies with the number of address writing
simultaneous 128-byte write.
cycles (n).
Number
of Cycles
1+n
129
2
2
Memory
MAT to be
Accessed
User MAT
User boot
MAT
User MAT
User boot
MAT
User MAT
User boot
MAT
Common to
both MATs
Mode
Write
Write
Write
Write
Write
Write
Write
1st Cycle
Address
X
X
X
X
X
X
X
Data
H'00
H'05
H'40
H'45
H'20
H'25
H'71
Mode
Read
Write
Write
Write
Address
RA
WA
X
X
2nd Cycle
Data
Dout
Din
H'20
H'25
H'71
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