DF2315VTE25 Renesas Electronics America, DF2315VTE25 Datasheet - Page 765
DF2315VTE25
Manufacturer Part Number
DF2315VTE25
Description
MCU 3V 384K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2315VTE25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2315VTE25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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[15] After programming finishes, clear FKEY and specify software protection.
Erasing Procedure in User Program Mode: The procedures for download, initialization, and
erasing are shown in figure 17.71.
The procedure program must be executed in an area other than the user MAT to be erased.
Especially the part where the SCO bit in FCCS is set to 1 for downloading must be executed in on-
chip RAM.
The area that can be executed in the steps of the user procedure program (on-chip RAM, user
MAT, and external space) is shown in section 17.29.3, Procedure Program and Storable Area for
Programming Data.
For the downloaded on-chip program area, refer to the RAM map for programming/erasing in
figure 17.69.
If this LSI is restarted by a power-on reset immediately after user MAT programming has
finished, secure a reset period (period of RES = 0) that is at least as long as normal 100 μs.
to be downloaded and set
JSR FTDAR setting+32
Select on-chip program
Start erasing procedure
download destination
Set the FPEFEQ and
FUBRA parameters
Set SCO to 1 and
execute download
Set FKEY to H'A5
Clear FKEY to 0
FPFR=0 ?
Initialization
DPFR = 0?
by FTDAR
program
1
Yes
Yes
Initialization error processing
Download error processing
No
No
Figure 17.71 Erasing Procedure
(a)
Rev.7.00 Feb. 14, 2007 page 731 of 1108
No
JSR FTDAR setting+16
Disable interrupts and
bus master operation
Set FEBS parameter
procedure program
Set FKEY to H'5A
Clear FKEY to 0
other than CPU
Required block
End erasing
FPFR=0 ?
completed?
erasing is
Erasing
1
Yes
Yes
Clear FKEY and erasing
REJ09B0089-0700
No
error processing
Section 17 ROM
(b)
(c)
(d)
(e)
(f)
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