DF2315VTE25 Renesas Electronics America, DF2315VTE25 Datasheet - Page 529
DF2315VTE25
Manufacturer Part Number
DF2315VTE25
Description
MCU 3V 384K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2315VTE25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2315VTE25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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• Reception
Receive operation should be stopped (by clearing RE to 0) before making a module stop mode
or software standby mode transition. RSR, RDR, and SSR are reset. If a transition is made
without stopping operation, the data being received will be invalid.
To continue receiving without changing the reception mode after the relevant mode is cleared,
set RE to 1 before starting reception. To receive with a different receive mode, the procedure
must be started again from initialization.
Figure 12.26 shows a sample flowchart for mode transition during reception.
Read TEND flag in SSR
Figure 12.23 Sample Flowchart for Mode Transition during Transmission
<Start of transmission>
Transition to software
standby mode, etc.
standby mode, etc.
Exit from software
operating mode?
<Transmission>
Yes
Yes
Yes
transmitted?
Initialization
TEND = 1
Change
All data
TE = 0
No
No
No
[1]
[2]
[3]
TE = 1
Section 12 Serial Communication Interface (SCI)
[1] Data being transmitted is interrupted.
[2] If TIE and TEIE are set to 1, clear
[3] Includes module stop mode.
After exiting software standby mode,
etc., normal CPU transmission is
possible by setting TE to 1, reading
SSR, writing TDR, and clearing
TDRE to 0, but note that if the DTC
has been activated, the remaining
data in DTCRAM will be transmitted
when TE and TIE are set to 1.
them to 0 in the same way.
Rev.7.00 Feb. 14, 2007 page 495 of 1108
REJ09B0089-0700
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