DF2315VTE25 Renesas Electronics America, DF2315VTE25 Datasheet - Page 455
DF2315VTE25
Manufacturer Part Number
DF2315VTE25
Description
MCU 3V 384K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2315VTE25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2315VTE25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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11.2.3
Note: * Only 0 can be written, to clear the flag.
RSTCSR is an 8-bit readable/writable * register that controls the generation of the internal reset
signal when TCNT overflows, and selects the type of internal reset signal.
RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal
reset signal caused by overflows.
Note: * RSTCSR is write-protected by a password to prevent accidental overwriting. For details
Bit 7—Watchdog Timer Overflow Flag (WOVF): Indicates that TCNT has overflowed
(changed from H'FF to H'00) during watchdog timer operation. This bit is not set in interval timer
mode.
Bit 7
WOVF
0
1
Bit 6—Reset Enable (RSTE): Specifies whether or not a reset signal is generated in the chip if
TCNT overflows during watchdog timer operation.
Bit 6
RSTE
0
1
Note: * The modules within the chip are not reset, but TCNT and TCSR within the WDT are reset.
Bit
Initial value :
R/W
see section 11.2.4, Notes on Register Access.
Reset Control/Status Register (RSTCSR)
Description
[Clearing condition]
Cleared by reading RSTCSR when WOVF = 1, then writing 0 to WOVF
[Setting condition]
Set when TCNT overflows (changes from H'FF to H'00) during watchdog timer
operation
Description
Reset signal is not generated if TCNT overflows *
Reset signal is generated if TCNT overflows
:
:
R/(W) *
WOVF
7
0
RSTE
R/W
6
0
R/W
—
5
0
—
—
4
1
Rev.7.00 Feb. 14, 2007 page 421 of 1108
—
—
3
1
Section 11 Watchdog Timer
—
—
2
1
REJ09B0089-0700
—
—
1
1
(Initial value)
(Initial value)
—
—
0
1
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