MCHC908RF2MFAE Freescale Semiconductor, MCHC908RF2MFAE Datasheet - Page 157
MCHC908RF2MFAE
Manufacturer Part Number
MCHC908RF2MFAE
Description
IC MCU 2K FLASH 4MHZ 32-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC68HC908RF2CFA.pdf
(188 pages)
Specifications of MCHC908RF2MFAE
Core Processor
HC08
Core Size
8-Bit
Speed
4MHz
Peripherals
LVD, POR, PWM, RF Mod
Number Of I /o
12
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
32-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCHC908RF2MFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Data Sheet — MC68HC908RF2
13.1 Introduction
13.2 Break Module (BRK)
13.2.1 Functional Description
MC68HC908RF2 — Rev. 4.0
MOTOROLA
This section describes the break module, the monitor module (MON), and the
monitor mode entry methods.
The break module can generate a break interrupt that stops normal program flow
at a defined address to enter a background program.
Features include:
When the internal address bus matches the value written in the break address
registers, the break module issues a breakpoint signal to the CPU. The CPU then
loads the instruction register with a software interrupt instruction (SWI) after
completion of the current CPU instruction. The program counter vectors to $FFFC
and $FFFD ($FEFC and $FEFD in monitor mode).
These events can cause a break interrupt to occur:
When a CPU-generated address matches the contents of the break address
registers, the break interrupt begins after the CPU completes its current instruction.
A return-from-interrupt instruction (RTI) in the break routine ends the break
interrupt and returns the MCU to normal operation.
structure of the break module.
•
•
•
•
•
•
Accessible input/output (I/O) registers during break interrupts
CPU-generated break interrupts
Software-generated break interrupts
COP disabling during break interrupts
A CPU-generated address (the address in the program counter) matches
the contents of the break address registers.
Software writes a 1 to the BRKA bit in the break status and control register.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Development Support
Section 13. Development Support
Figure 13-1
shows the
Data Sheet
157
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