MCF5307FT90B Freescale Semiconductor, MCF5307FT90B Datasheet - Page 78
MCF5307FT90B
Manufacturer Part Number
MCF5307FT90B
Description
IC MPU 32BIT COLDF 90MHZ 208FQFP
Manufacturer
Freescale Semiconductor
Series
MCF530xr
Datasheets
1.MCF5307AI66B.pdf
(484 pages)
2.MCF5307AI66B.pdf
(16 pages)
3.MCF5307AI66B.pdf
(2 pages)
Specifications of MCF5307FT90B
Core Processor
Coldfire V3
Core Size
32-Bit
Speed
90MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, POR, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
208-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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CMPI
DIVS
DIVU
EOR
EORI
EXT
EXTB
HALT
JMP
JSR
LEA
LINK
LSL
LSR
MAC
MACL
MOVE
MOVE from
MAC
MOVE to
MAC
MOVE from
CCR
MOVE to
CCR
MOVEA
Instruction
Instruction Set Summary
2-38
1
<ea>y,Dx
<ea-1>y,Dx
<ea>y,Dx
<ea-1>y,Dx
Dy,<ea>x
Dy,<ea>x
#<data>,Dx
#<data>,Dx
Dx
None
<ea-3>y
<ea-3>y
<ea-3>y,Ax
Ax,#<d16>
Dy,Dx
#<data>,Dx
Dy,Dx
#<data>,Dx
Ry,RxSF
Ry,RxSF,<ea-1>y,Rw
<ea>y,<ea>x
MASK,Rx
ACC,Rx
MACSR,Rx
MACSR,CCR
Ry,ACC
Ry,MACSR
Ry,MASK
#<data>,ACC
#<data>,MACSR
#<data>,MASK
CCR,Dx
Dy,CCR
#<data>,CCR
<ea>y,Ax
Operand Syntax
Table 2-7. User-Mode Instruction Set Summary (Continued)
Freescale Semiconductor, Inc.
For More Information On This Product,
.L
.W
.L
.W
.L
.L
.L
.B →.W
.W →.L
.B →.L
Unsized
Unsized
Unsized
.L
.W
.L
.L
.L
.L
.L + (.W × .W) → .L
.L + (.L × .L) → .L
.L + (.W × .W) → .L, .L
.L + (.L × .L) → .L, .L
.B,.W,.L
.L
.L
.L
.L
.W
.B
.W,.L → .L
Operand Size
Go to: www.freescale.com
MCF5307 User’s Manual
Destination – immediate data
Dx /<ea>y → Dx {16-bit remainder; 16-bit quotient}
Dx /<ea>y → Dx {32-bit quotient}
Signed operation
Dx /<ea>y → Dx {16-bit remainder; 16-bit quotient}
Dx /<ea>y → Dx {32-bit quotient}
Unsigned operation
Source ^ destination → destination
Immediate data ^ destination → destination
Sign-extended destination → destination
Sign-extended destination → destination
Enter halted state
Address of <ea> → PC
SP – 4 → SP; next sequential PC → (SP); <ea> → PC
<ea> → Ax
SP – 4 → SP; Ax → (SP); SP → Ax; SP + d16 → SP
X/C ← (Dx << Dy) ← 0
X/C ← (Dx << #<data>) ← 0
0 → (Dx >> Dy) → X/C
0 → (Dx >> #<data>) → X/C
ACC + (Ry × Rx){<< 1 | >> 1} → ACC
ACC + (Ry × Rx){<< 1 | >> 1} → ACC; (<ea>y{&MASK}) →
Rw
ACC + (Ry × Rx){<< 1 | >> 1} → ACC
ACC + (Ry × Rx){<< 1 | >> 1} → ACC; (<ea-1>y{&MASK})
→ Rw
<ea>y → <ea>x
Rm → Rx
MACSR → CCR
Ry → Rm
#<data> → Rm
CCR → Dx
Dy → CCR
#<data> → CCR
Source → destination
Operation
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