MCF5307FT90B Freescale Semiconductor, MCF5307FT90B Datasheet - Page 205
MCF5307FT90B
Manufacturer Part Number
MCF5307FT90B
Description
IC MPU 32BIT COLDF 90MHZ 208FQFP
Manufacturer
Freescale Semiconductor
Series
MCF530xr
Datasheets
1.MCF5307AI66B.pdf
(484 pages)
2.MCF5307AI66B.pdf
(16 pages)
3.MCF5307AI66B.pdf
(2 pages)
Specifications of MCF5307FT90B
Core Processor
Coldfire V3
Core Size
32-Bit
Speed
90MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, POR, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
208-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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8.3 I
The I
For I
open collector outputs. (There is no such requirement for inputs.) The logic AND function
is exercised on both lines with external pull-up resistors.
Out of reset, the I
or responding to a slave transmit address, the I
receiver state. See Section 8.6.1, “Initialization Sequence,” for exceptions.
8.4 I
Normally, a standard communication is composed of the following parts:
1. START signal—When no other device is bus master (both SCL and SDA lines are
SCL
2. Slave address transmission—The master sends the slave address in the first byte
A
SDA
2
2
C compliance, all devices connected to these two signals must have open drain or
C module uses a serial data line (SDA) and a serial clock line (SCL) for data transfer.
START
Signal
at logic high), a device can initiate communication by sending a START signal (see
A in Figure 8-2). A START signal is defined as a high-to-low transition of SDA
while SCL is high. This signal denotes the beginning of a data transfer (each data
transfer can be several bytes long) and awakens all slaves.
after the START signal (B). After the seven-bit calling address, it sends the R/W bit
(C), which tells the slave data transfer direction.
Each slave must have a unique address. An I
that is the same as its slave address; it cannot be master and slave at the same time.
2
2
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
C System Configuration
C Protocol
msb
1
The I
I
protocol, and restrictions, see The I
Version 2.1.
2
2
C bus protocol. For information on system configuration,
Calling Address
2
Figure 8-2. I
3
C default is as slave receiver. Thus, when not programmed to be a master
2
C module is designed to be compatible with the Philips
B
4
Freescale Semiconductor, Inc.
5
For More Information On This Product,
6
2
C Standard Communication Protocol
7
Go to: www.freescale.com
Chapter 8. I
R/W ACK
lsb
8
C
Bit
9
NOTE:
D
XXX
2
C Module
2
C module should return to the default slave
msb
D7 D6 D5
1
2
E
C master must not transmit an address
2
C Bus Specification,
2
3
Data Byte
D4 D3 D2 D1 D0
4
5
I
2
C System Configuration
6
7
lsb
8
ACK
No
Bit
9
STOP
Signal
F
8-3
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