ST10F271Z1T3 STMicroelectronics, ST10F271Z1T3 Datasheet
ST10F271Z1T3
Specifications of ST10F271Z1T3
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ST10F271Z1T3 Summary of contents
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... PWM unit + 4-channel XPWM ■ A/D converter Order Codes Order code Package ST10F271Z1Q3 PQFP144 ST10F271Z1T3 LQFP144 January 2008 PQFP144 ( 3.4mm) (Plastic Quad Flat Package) – 24-channel 10-bit – 3 µs minimum conversion time ■ Serial channels – Two synch. / asynch. serial channels – ...
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Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST10F271Z1 5.5.6 5.5.7 5.5.8 5.5.9 5.6 Write operation examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 13.2 I/O’s special features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST10F271Z1 21.2 Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 25.7 A/D converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 25.7.1 ...
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ST10F271Z1 List of tables Table 1. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables Table 49. Reset event ...
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ST10F271Z1 List of figures Figure 1. Logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures Figure 49. ST10F271Z1 PLL jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... ST10F271Z1 1 Introduction The ST10F271Z1 device is a derivative of the STMicroelectronics ST10 family of 16-bit single-chip CMOS microcontrollers. The ST10F271Z1 combines high CPU performance ( million instructions per second) with high peripheral functionality and enhanced I/O-capabilities. It also provides on- chip high-speed single voltage Flash memory, on-chip high-speed RAM, and clock generation via PLL. The ST10F271Z1 is processed in 0.18 µ ...
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Pin data 2 Pin data Figure 2. Pin configuration (top view) P6.0 / CS0 P6.1 / CS1 P6.2 / CS2 P6.3 / CS3 P6.4 / CS4 P6.5 / HOLD / SCLK1 P6.6 / HLDA / MTSR1 P6.7 / BREQ / ...
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ST10F271Z1 Table 1. Pin description Symbol Pin Type I ... ... 5 O P6 I/O 9-16 I/O I ... ... I/O 12 P8.0 ...
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Pin data Table 1. Pin description (continued) Symbol Pin Type 19-26 I P7.0 - P7.7 ... ... I/O ... ... 26 I/O 27-36 I 39- P5 P5.10 - ...
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ST10F271Z1 Table 1. Pin description (continued) Symbol Pin Type 65-70, I/O 73-80, I P3 P3.6 - P3.13, P3. I/O ...
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Pin data Table 1. Pin description (continued) Symbol Pin Type 85-92 I P4.0 –P4 ...
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ST10F271Z1 Table 1. Pin description (continued) Symbol Pin Type STBY P0L.0 -P0L.7, 100-107, P0H.0 108, I/O P0H.1 - 111-117 P0H.7 118-125 I/O 128-135 P1L.0 - P1L.7 P1H.0 - P1H.7 132 I 133 I 134 I ...
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Pin data Table 1. Pin description (continued) Symbol Pin Type XTAL1 138 I XTAL2 137 O XTAL3 143 I XTAL4 144 O RSTIN 140 I RSTOUT 141 O NMI 142 AREF AGND RPD ...
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ST10F271Z1 3 Functional description The architecture of the ST10F271Z1 combines advantages of both RISC and CISC processors and an advanced peripheral subsystem. The block diagram gives an overview of the different on-chip components and the high bandwidth internal bus structure ...
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Memory organization 4 Memory organization The memory space of the ST10F271Z1 is configured in a unified memory architecture. Code memory, data memory, registers and I/O ports are organized within the same linear address space of 16 Mbytes. The entire memory ...
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ST10F271Z1 external memory interface, using the BUSCONx register corresponding to address matching ADDRSELx register. After reset the XRAM2 is mapped from address 09’0000h. XRAM2 represents also the Stand-by RAM, which can be maintained biased through pin when ...
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Memory organization SSC1: Address range 00’E800h - 00’E8FFh is reserved for the SSC1 Module access. The SSC1 is enabled by setting XPEN bit 2 of the SYSCON register and bit 8 of the XPERCON register. Accesses to the SSC1 Module ...
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ST10F271Z1 Figure 4. ST10F271Z1 on-chip memory mapping (ROMEN=1 / XADRS = 800Bh - reset value) Data Code Code Page Segment Segment FF FFFF 1023 11 FFFF 255 17 Ext. Memory 11 0000 10 FFFF 16 Ext. Memory 10 0000 0F ...
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Internal Flash memory 5 Internal Flash memory 5.1 Overview The on-chip Flash is composed by one matrix module, 128 Kbytes wide. This module is on ST10 Internal bus called IFlash Figure 5. Flash structure The programming operations ...
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ST10F271Z1 application mapping. Accesses to this address range will send back the content of the Flash cell (by default FFFFh, blank value when the device is delivered) 2 Accesses to the area will send back the value 009Bh. 5.2.2 Module ...
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Internal Flash memory The table above refers to the configuration when bit ROMS1 of SYSCON register is set. When Bootstrap mode is entered: ● Test-Flash is seen and available for code fetches (address 00’0000h) ● User I-Flash is only available ...
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ST10F271Z1 5.3 Write operation The Flash module have one single register interface mapped in the memory space of the IBUS (0x08 0000 to 0x08 0015). All the operations are enabled through four 16-bit control registers: Flash Control Register 1-0 High/Low ...
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Internal Flash memory Table 7. Flash control register 0 low Bit Bank 0 Busy (IFlash) This bit indicates that a write operation is running on Bank 0 (IFlash automatically set when bit WMS is set. Setting Protection operation ...
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ST10F271Z1 Table 8. Flash control register 0 high Bit Set Protection This bit must be set to select the Set Protection operation. The Set Protection operation allows to program 0s in place the Flash non-volatile protection registers. ...
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Internal Flash memory Table 8. Flash control register 0 high (continued) Bit Suspend This bit must be set to suspend the current Program (Word or Double Word) or Sector Erase operation in order to read data in one of the ...
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ST10F271Z1 5.4.4 Flash control register 1 high The Flash Control Register 1 High (FCR1H), together with Flash Control Register 1 Low (FCR1L), is used to select the Sectors to Erase, or during any write operation to monitor the status of ...
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Internal Flash memory Table 12. Flash data register 0 low Bit Data Input 15:0 These bits must be written with the Data to program the Flash with the following DIN(15:0) operations: Word Program (32-bit), Double Word Program (64-bit) and Set ...
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ST10F271Z1 Table 15. Flash data register 1 high Bit Data input 31:16 These bits must be written with the data to program the Flash with the following DIN(31:16) operations: word program (32-bit), double word program (64-bit) and set protection. 5.4.9 ...
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Internal Flash memory 5.4.11 Flash error register Flash error register, as well as all the other Flash registers, can be properly read only once LOCK bit of register FCR0L is low. Nevertheless, its content is updated when also BSY0 bit ...
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ST10F271Z1 5.5 Protection strategy The protection bits are stored in non-volatile Flash cells inside IFlash module, that are read once at reset and stored in 4 Volatile registers. Before they are read from the non-volatile cells, all the available protections ...
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... Test Interface. If programmed the contrary, all the DBGP debug features, the Test Interface and all the Flash test modes are disabled. Even STMicroelectronics will not be able to access the device to run any eventual failure analysis. 5.5.4 Flash non-volatile access protection register 1 low ...
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ST10F271Z1 5.5.6 XBus Flash volatile temporary access unprotection register (XFVTAUR0) XFVTAUR0 (0x00 EB50 Table 23. XBus Flash volatile temporary access unprotection register Bit Temporary access unprotection bit If this bit is set to 1, the access protection ...
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Internal Flash memory Figure 6. Summary of access protection level Fetching from IFlash Fetching from IRAM Fetching from XRAM Fetching from external memory When the Access Protection is enabled, Flash registers can not be written program/erase operation can ...
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ST10F271Z1 Note: The write operation commands must be executed from another memory (internal RAM or external memory ST10F269 device. In fact, due to IBus characteristics not possible to perform write operation in Flash while fetching code ...
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Internal Flash memory Then the operation can be resumed in the following way: FCR0H |= 0x0800; FCR0H |= 0x8000; Before resuming a suspended erase, FCR1H/FCR1L must be read to check if the erase is already completed (FCR1H = FCR1L = ...
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ST10F271Z1 FCR0H |= 0x0100; FARL = 0xDFB4; FARH = 0x0008; FDR0L = 0xFFF0; FDR0H = 0xFFFF; FCR0H |= 0x8000; Example 2: Enable access and debug protection. FCR0H |= 0x0100; FARL = 0xDFB8; FARH = 0x0008; FDR0L = 0xFFFC; FCR0H |= ...
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Internal Flash memory Table 24. Flash write operations Operation Word program (32-bit) Double word program (64-bit) Sector erase Set protection Program/erase suspend 42/185 Select bit Address and data FARL/FARH WPG FDR0L/FDR0H FARL/FARH DWPG FDR0L/FDR0H FDR1L/FDR1H SER FCR1L/FCR1H SPR FDR0L/FDR0H SUSP ...
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ST10F271Z1 6 Bootstrap loader ST10F271Z1 implements boot capabilities in order to: ● Support bootstrap via UART or bootstrap via CAN for the standard bootstrap. ● Support a selective bootstrap loader, to manage the bootstrap sequence in a different way. 6.1 ...
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Bootstrap loader 6.3 Alternate and selective boot mode (ABM and SBM) 6.3.1 Activation of the ABM and SBM Alternate boot is activated with the combination ‘01’ on Port0L[5..4] at the rising edge of RSTIN. 6.3.2 User mode signature integrity check ...
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ST10F271Z1 7 Central processing unit (CPU) The CPU includes a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been added for a separate multiply and divide unit, a bit-mask generator and a ...
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Central processing unit (CPU) 7.1 Multiplier-accumulator unit (MAC) The MAC co-processor is a specialized co-processor added to the ST10 CPU Core in order to improve the performances of the ST10 Family in signal processing algorithms. The standard ST10 CPU has ...
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ST10F271Z1 Table 26. Standard instruction set summary Mnemonic ADD(B) ADDC(B) SUB(B) SUBC(B) MUL(U) DIV(U) DIVL(U) CPL(B) NEG(B) AND(B) OR(B) XOR(B) BCLR BSET BMOV(N) BAND, BOR, BXOR BCMP BFLDH/L CMP(B) CMPD1/2 CMPI1/2 PRIOR SHL / SHR ROL / ROR ASHR MOV(B) ...
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Central processing unit (CPU) Table 26. Standard instruction set summary (continued) Mnemonic CALLA, CALLI, CALLR CALLS PCALL TRAP PUSH, POP SCXT RET RETS RETP RETI SRST IDLE PWRDN SRVWDT DISWDT EINIT ATOMIC EXTR EXTP(R) EXTS(R) NOP 7.3 MAC co-processor specific ...
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ST10F271Z1 Table 27. MAC instruction set summary (continued) Mnemonic CoLOAD(-,2) CoMAC(R,u,s,-,rnd) CoMACM(R)(u,s,-,rnd) CoMAX / CoMIN CoMOV CoMUL(u,s,-,rnd) CoNEG(rnd) CoNOP CoRND CoSHL / CoSHR CoSTORE CoSUB(2,R) Central processing unit (CPU) Description Load accumulator with operands (Un)Signed/(un)signed multiply-accumulate & optional round (Un)Signed/(un)Signed ...
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External bus controller 8 External bus controller All of the external memory accesses are performed by the on-chip external bus controller. The EBC can be programmed to single chip mode when no external memory is required one of ...
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ST10F271Z1 9 Interrupt system The interrupt response time for internal program execution is from 187 MHz CPU clock. The ST10F271Z1 architecture supports several mechanisms for fast and flexible response to service requests that can ...
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Interrupt system Table 28. Interrupt sources (continued) Source of interrupt or PEC service request CAPCOM register 6 CAPCOM register 7 CAPCOM register 8 CAPCOM register 9 CAPCOM register 10 CAPCOM register 11 CAPCOM register 12 CAPCOM register 13 CAPCOM register ...
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ST10F271Z1 Table 28. Interrupt sources (continued) Source of interrupt or PEC service request GPT2 timer 6 GPT2 CAPREL register A/D conversion complete A/D overrun error ASC0 transmit ASC0 transmit buffer ASC0 receive ASC0 error SSC transmit SSC receive SSC error ...
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Interrupt system available vector. If more than one source is enabled to issue the request, the service routine will have to take care to identify the real event to be serviced. This can easily be done by checking the flag ...
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ST10F271Z1 Table 29. X-Interrupt detailed mapping (continued) ASC1 error PLL unlock / OWD PWM1 channel 3...0 9.2 Exception and error traps list Table 30 shows all of the possible exceptions or error conditions that can arise during run- time. Table ...
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Capture / compare (CAPCOM) units 10 Capture / compare (CAPCOM) units The ST10F271Z1 has two 16-channel CAPCOM units which support generation and control of timing sequences channels with a maximum resolution of 125 ...
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ST10F271Z1 Table 31. Compare modes Compare modes Interrupt-only compare mode; several compare interrupts per timer period are Mode 0 possible Pin toggles on each compare match; several compare events per timer period are Mode 1 possible Interrupt-only compare mode; only ...
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General purpose timer unit 11 General purpose timer unit The GPT unit is a flexible multifunctional timer/counter structure which is used for time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or ...
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ST10F271Z1 Table 35. GPT1 timer input frequencies, resolutions and periods at 64 MHz MHz CPU 000b Prescaler factor 8 Input freq 8 MHz Resolution 125 ns Period maximum 8.2 ms 16.4 ms Figure 10. Block diagram of ...
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General purpose timer unit Table 36 and Table 37 prescaler option at 40MHz and 64MHz CPU clock respectively. Table 36. GPT2 timer input frequencies, resolutions and periods at 40 MHz MHz CPU 000b Prescaler factor 4 Input ...
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ST10F271Z1 12 PWM modules Two pulse width modulation modules are available on ST10F271Z1: standard PWM0 and XBus PWM1. They can generate up to four PWM output signals each, using edge-aligned or centre-aligned PWM. In addition, the PWM modules can generate ...
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Parallel ports 13 Parallel ports 13.1 Introduction The ST10F271Z1 MCU provides up to 111 I/O lines with programmable features. These capabilities bring very flexible adaptation of this MCU to wide range of applications. ST10F271Z1 has nine groups of I/O lines ...
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ST10F271Z1 13.2.2 Input threshold control The standard inputs of the ST10F271Z1 determine the status of input signals according to TTL levels. In order to accept and recognize noisy signals, CMOS input thresholds can be selected instead of the standard TTL ...
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Parallel ports This is done by setting or clearing the direction control bit DPx.y of the pin before enabling the alternate function. There are port lines, however, where the direction of the port line is switched automatically. For instance, in ...
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ST10F271Z1 14 A/D converter A 10-bit A/D converter with 16+8 multiplexed input channels and a sample and hold circuit is integrated on-chip. An automatic self-calibration adjusts the A/D converter module to process parameter variations at each reset event. The sample ...
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A/D converter register. The data can be transferred to the RAM by interrupt software management or using the PEC data transfer. ● Wait for ADDAT read mode: When using continuous modes, in order to avoid to overwrite the result of ...
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ST10F271Z1 15 Serial channels Serial communication with other microcontrollers, microprocessors, terminals or external peripheral components is provided four serial interfaces: two asynchronous / synchronous serial channels (ASC0 and ASC1) and two high-speed synchronous serial channel (SSC0 and ...
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Serial channels Table 41. ASC asynchronous baud rates by reload value and deviation errors (f S0BRS = ‘0’, f CPU Baud rate (baud) Deviation error 2 000 000 0.0% / 0.0% 112 000 +1.5% / -7.0% 56 000 +1.5% / ...
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ST10F271Z1 Table 42. ASC synchronous baud rates by reload value and deviation errors (f S0BRS = ‘0’, f CPU Deviation Baud rate (baud) error 900 0.0% / 0.0% 612 0.0% / 0.0% Table 43. ASC synchronous baud rates by reload ...
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Serial channels Table 44 and Table 45 the resulting bit times for 40 MHz and 64 MHz CPU clock respectively. The maximum is anyway limited to 8 Mbaud. Table 44. SSC synchronous baud rate and reload values (f Baud rate ...
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ST10F271Z1 16 I2C interface 2 The integrated I C Bus Module handles the transmission and reception of frames over the two-line SDA/SCL in accordance with the I operate in slave mode, in master mode or in multi-master mode. It can ...
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CAN modules 17 CAN modules The two integrated CAN modules (CAN1 and CAN2) are identical and handle the completely autonomous transmission and reception of CAN frames according to the CAN specification V2.0 part B (active based on the ...
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ST10F271Z1 Single CAN bus The single CAN Bus multiple interfaces configuration may be implemented using two CAN transceivers as shown in Figure 13. Connection to single CAN bus via separate CAN transceivers CAN_H CAN_L The ST10F271Z1 also supports single CAN ...
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CAN modules Figure 15. Connection to two different CAN buses (e.g. for gateway application) CAN_H CAN_L Parallel Mode In addition to previous configurations, a parallel mode is supported. This is shown in Figure 16. Figure 16. Connection to one CAN ...
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ST10F271Z1 18 Real-time clock The Real-Time Clock is an independent timer, in which the clock is derived directly from the clock oscillator on XTAL1 (main oscillator) input or XTAL3 input (32 kHz low-power oscillator) so that it can be kept ...
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Watchdog timer 19 Watchdog timer The Watchdog timer is a fail-safe mechanism which prevents the microcontroller from malfunctioning for long periods of time. The Watchdog Timer is always enabled after a reset of the chip and can only be disabled ...
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ST10F271Z1 20 System reset System reset initializes the MCU in a predefined state. There are six ways to activate a reset state. The system start-up configuration is different for each case as shown in Table 48. Reset event definition Reset ...
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System reset all internal/external bus cycles, it switches buses (data, address and control signals) and I/O pin drivers to high-impedance, it pulls high Port0 pins. Note asynchronous reset occurs during a read or write phase in internal memories, ...
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ST10F271Z1 In next Figures 17 respectively with boot from internal or external memory, highlighting the reset phase extension introduced by the embedded Flash module when selected. Note: Never power the device without keeping RSTIN pin grounded: the device could enter ...
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System reset Figure 18. Asynchronous power-on RESET ( XTAL1 RPD RSTIN RSTF (After Filter) P0[15:13] P0[12:2] P0[1:0] ALE RST Note TCL depending on clock source selection. Hardware reset The asynchronous ...
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ST10F271Z1 Figure 19. Asynchronous hardware reset ( RPD RSTIN RSTF (After Filter) P0[15:13] P0[12:2] P0[1:0] IBUS-CS (internal) FLARST RST Note 1. Longer than Port0 settling time + PLL synchronization (if needed, that is P0(15:13) changed) Longer than 500 ...
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System reset Figure 20. Asynchronous hardware reset ( RPD RSTIN RSTF (After Filter) P0[15:13] P0[12:2] P0[1:0] ALE RST Note 1. Longer than Port0 settling time + PLL synchronization (if needed, that is P0(15:13) changed) Longer than 500ns to ...
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ST10F271Z1 Short and long synchronous reset Once the first maximum 16 TCL are elapsed (4+12 TCL), the internal reset sequence starts 1024 TCL cycles long: at the end of it, and after other 8 TCL the level of ...
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System reset Synchronous reset and RPD pin Whenever the RSTIN pin is pulled low (by external hardware consequence of a Bidirectional reset), the RPD internal weak pull-down is activated. The external capacitance (if any) on RPD pin ...
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ST10F271Z1 Figure 21. Synchronous short / long hardware RESET ( ≤4 TCL RSTIN ≥ ≤ 500 ns RSTF (After Filter) P0[15:13] P0[12:2] P0[1:0] IBUS-CS (Internal) FLARST RST RSTOUT RPD Notes: 1. RSTIN assertion can be released ...
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System reset Figure 22. Synchronous short / long hardware reset ( RSTIN RSTF (After Filter) P0[15:13] P0[12:2] P0[1:0] ALE RST RSTOUT RPD Notes: 1. RSTIN assertion can be released there. Refer also to Section 21.1 for details on ...
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ST10F271Z1 Figure 23. Synchronous long hardware reset ( RSTIN RSTF (After Filter) P0[15:13] P0[12:2] P0[1:0] IBUS-CS (Internal) FLARST RST RSTOUT RPD Notes during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about ...
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System reset Figure 24. Synchronous long hardware reset ( TCL RSTIN ≥ ≤ 500 ns RSTF (After Filter) P0[15:13] P0[12:2] P0[1:0] ALE RST RSTOUT RPD Notes during the reset condition (RSTIN low), RPD ...
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ST10F271Z1 Refer to next Figures 29 for bidirectional. 20.5 Watchdog timer reset When the watchdog timer is not disabled during the initialization, or serviced regularly during program execution, it will overflow and trigger the reset sequence. Unlike hardware and software ...
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System reset Figure 26 WDT unidirectional reset ( RSTIN P0[15:13] P0[12:8] P0[7:2] P0[1:0] ALE RST RSTOUT 20.6 Bidirectional reset As shown in the previous sections, the RSTOUT pin is driven active (low level) at the beginning ...
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ST10F271Z1 The Bidirectional reset is not effective in case RPD is held low, when a Software or Watchdog reset event occurs. On the contrary Software or Watchdog Bidirectional reset event is active and RPD becomes low, the RSTIN ...
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System reset Figure 27 WDT bidirectional RESET (EA=1) RSTIN RSTF (After Filter) P0[15:13] P0[12:8] P0[7:2] P0[1:0] IBUS-CS (Internal) FLARST RST RSTOUT 92/185 ≥ ≥ ≤ 500 ns ≤ 500 ns not transparent transparent not ...
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ST10F271Z1 Figure 28 WDT bidirectional reset ( RSTIN ≥ ≤ 500 ns RSTF (After Filter) P0[15:13] P0[12:8] P0[7:2] P0[1:0] ALE RST RSTOUT ≥ ≤ 500 ns not transparent not t. transparent not ...
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System reset Figure 29 WDT bidirectional reset (EA=0) followed RESET RSTIN RSTF (After Filter) P0[15:13] P0[12:8] P0[7:2] P0[1:0] ALE RST RSTOUT 20.7 Reset circuitry Internal reset circuitry is described in resistor of 50 kΩ to ...
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ST10F271Z1 To ensure correct power-up reset with controlled supply current consumption, specially if clock signal requires a long period of time to stabilize, an asynchronous hardware reset is required during power-up. For this reason recommended to connect the ...
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System reset Figure 31. System reset circuit ST10F271Z1 Figure 32. Internal (simplified) reset circuitry Internal Reset Signal 96/185 External Hardware RSTIN o.d. R0 Open Drain Inverter RPD + C0 EINIT Instruction Clr Q Set ...
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ST10F271Z1 20.8 Reset application examples Next two timing diagrams bidirectional internal reset events (software and watchdog) including in particular the external capacitances charge and discharge transients (refer also to external circuit scheme). Figure 33. Example of software or watchdog bidirectional ...
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System reset Figure 34. Example of software or watchdog bidirectional reset ( 98/185 ST10F271Z1 ...
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ST10F271Z1 20.9 Reset summary A summary of the different reset events is reported in the table below. Table 49. Reset event Event Asynch. Power-on reset Asynch ...
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System reset Table 49. Reset event (continued) Event Synch Synch. (2) Software reset Synch Synch Synch Synch. (2) Watchdog reset 0 1 ...
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ST10F271Z1 Figure 35. PORT0 bits latched into the different registers after reset H.7 H.6 CLKCFG RP0H CLKCFG Clock Generator P0L.7 ROMEN 10 9 PORT0 H.5 H.4 H.3 H.2 H.1 H.0 L.7 SALSEL CSSEL WRC BUSTYP CSSEL WRC SALSEL Port 4 ...
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Power reduction modes 21 Power reduction modes Three different power reduction modes with different levels of power reduction have been implemented in the ST10F271Z1. In Idle mode only CPU is stopped, while peripheral still operate. In power-down mode both CPU ...
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ST10F271Z1 Before entering power-down mode (by executing the instruction PWRDN), bit VREGOFF in XMISC register must be set. Note: Leaving the main voltage regulator active during power-down may lead to unexpected behavior (ex: CPU wake-up) and power consumption higher than ...
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Power reduction modes In normal running mode (that is when main V during reset to exercise the EA functionality associated with the same pin: the voltage supply for the circuitries which are usually biased with V oscillator used in conjunction ...
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ST10F271Z1 Warning: 21.3.2 Exiting stand-by mode After the system has entered the Stand-by Mode, the procedure to exit this mode consists of a standard Power-on sequence, with the only difference that the RAM is already powered through V internal reference ...
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Power reduction modes Table 51. Power reduction modes summary Mode Idle Power-down Stand-by 106/185 on on off off off off on on off off on on off off off on off off off on ...
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ST10F271Z1 22 Programmable output clock divider A specific register mapped on the XBUS allows to choose the division factor on the CLKOUT signal (P3.15). This register is mapped on X-Miscellaneous memory address range. When CLKOUT function is enabled by setting ...
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Register set 23 Register set This section summarizes all registers implemented in the ST10F271Z1, ordered by name. 23.1 Special function registers The following table lists all SFRs which are implemented in the ST10F271Z1 in alphabetical order. Bit-addressable SFRs are marked ...
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ST10F271Z1 Table 52. List of special function registers (continued) Physical Name address CC4 FE88h CC4IC b FF80h CC5 FE8Ah CC5IC b FF82h CC6 FE8Ch CC6IC b FF84h CC7 FE8Eh CC7IC b FF86h CC8 FE90h CC8IC b FF88h CC9 FE92h CC9IC ...
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Register set Table 52. List of special function registers (continued) Physical Name address CC21 FE6Ah CC21IC b F16Ah E CC22 FE6Ch CC22IC b F16Ch E CC23 FE6Eh CC23IC b F16Eh E CC24 FE70h CC24IC b F170h E CC25 FE72h CC25IC ...
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ST10F271Z1 Table 52. List of special function registers (continued) Physical Name address DP0H b F102h E DP1L b F104h E DP1H b F106h E DP2 b FFC2h DP3 b FFC6h DP4 b FFCAh DP6 b FFCEh DP7 b FFD2h DP8 ...
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Register set Table 52. List of special function registers (continued) Physical Name address ODP7 b F1D2h E ODP8 b F1D6h E ONES b FF1Eh P0L b FF00h P0H b FF02h P1L b FF04h P1H b FF06h P2 b FFC0h P3 ...
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ST10F271Z1 Table 52. List of special function registers (continued) Physical Name address PW1 FE32h PW2 FE34h PW3 FE36h PWMCON0 b FF30h PWMCON1 b FF32h PWMIC b F17Eh E QR0 F004h E QR1 F006h E QX0 F000h E QX1 F002h E ...
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Register set Table 52. List of special function registers (continued) Physical Name address T1 FE52h T1IC b FF9Eh T1REL FE56h T2 FE40h T2CON b FF40h T2IC b FF60h T3 FE42h T3CON b FF42h T3IC b FF62h T4 FE44h T4CON b ...
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ST10F271Z1 Table 52. List of special function registers (continued) Physical Name address XPERCON b F024h E ZEROS b FF1Ch Note: 1. The system configuration is selected during reset. SYSCON reset value is 0000 0xx0 x000 0000b. 2. Reset Value depends ...
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Register set Table 53. List of XBus registers (continued) Name CAN1IF2CR CAN1IF2DA1 CAN1IF2DA2 CAN1IF2DB1 CAN1IF2DB2 CAN1IF2M1 CAN1IF2M2 CAN1IF2MC CAN1IP1 CAN1IP2 CAN1IR CAN1MV1 CAN1MV2 CAN1ND1 CAN1ND2 CAN1SR CAN1TR CAN1TR1 CAN1TR2 CAN2BRPER CAN2BTR CAN2CR CAN2EC CAN2IF1A1 CAN2IF1A2 CAN2IF1CM CAN2IF1CR CAN2IF1DA1 CAN2IF1DA2 CAN2IF1DB1 ...
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ST10F271Z1 Table 53. List of XBus registers (continued) Name CAN2IF2A1 CAN2IF2A2 CAN2IF2CM CAN2IF2CR CAN2IF2DA1 CAN2IF2DA2 CAN2IF2DB1 CAN2IF2DB2 CAN2IF2M1 CAN2IF2M2 CAN2IF2MC CAN2IP1 CAN2IP2 CAN2IR CAN2MV1 CAN2MV2 CAN2ND1 CAN2ND2 CAN2SR CAN2TR CAN2TR1 CAN2TR2 I2CCCR1 I2CCCR2 I2CCR I2CDR I2COAR1 I2COAR2 I2CSR1 I2CSR2 RTCAH ...
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Register set Table 53. List of XBus registers (continued) Name RTCDL RTCH RTCL RTCPH RTCPL XCLKOUTDIV XEMU0 XEMU1 XEMU2 XEMU3 XIR0CLR XIR0SEL XIR0SET XIR1CLR XIR1SEL XIR1SET XIR2CLR XIR2SEL XIR2SET XIR3CLR XIR3SEL XIR3SET XMISC XP1DIDIS XPEREMU XPICON XPOLAR XPP0 XPP1 XPP2 ...
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ST10F271Z1 Table 53. List of XBus registers (continued) Name XPT3 XPW0 XPW1 XPW2 XPW3 XPWMCON0 XPWMCON0CLR XPWMCON0SET XPWMCON1 XPWMCON1CLR XPWMCON1SET XPWMPORT XS1BG XS1CON XS1CONCLR XS1CONSET XS1PORT XS1RBUF XS1TBUF XSSCBR XSSCCON XSSCCONCLR XSSCCONSET XSSCPORT XSSCRB XSSCTB 23.3 Flash registers ordered by ...
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Register set Table 54. List of Flash registers Name FARH FARL FCR0H FCR0L FCR1H FCR1L FDR0H FDR0L FDR1H FDR1L 0x0008 000C FER FNVAPR0 0x0008 DFB8 FNVAPR1H 0x0008 DFBE FNVAPR1L 0x0008 DFBC FNVWPIR 0x000E DFB0 XFVTAUR0 0x0000 EB50 23.4 Identification registers ...
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... ST10F271Z1 Table 55. IDMANUF Bit Manufacturer identifier MANUF 020h: STMicroelectronics manufacturer (JTAG worldwide normalization). IDCHIP (F07Ch / 3Eh Table 56. IDCHIP Bit Device identifier IDCHIP 110h: ST10F271Z1 identifier (272). Device revision identifier REVID Xh: According to revision number. IDMEM (F07Ah / 3Dh MEMTYP R Table 57. IDMEM Bit Internal memory size ...
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Register set IDPROG (F078h / 3Ch Table 58. IDPROG Bit Programming V PROGVDD V DD following formula: V PROGVPP Programming V Note: All identification words are read only registers. The values written inside different Identification Register bits ...
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ST10F271Z1 24 Known limitations This section describes all functional and electrical limitations identified on the silicon revision A of the ST10F271Z1. They are listed in The revision number of the device can be read in the IDCHIP register (@F07Ch) which ...
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Known limitations 24.1 Injected conversion stalling the ADC Description Whenever a new injection request occurs before the ADDAT2 register has been read by the CPU (that is, when the result of the previous injection request has not been read), the ...
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ST10F271Z1 not know that a new converted value is ready to be read in ADDAT2 register. Therefore at the following injection request the ADC fills the temporary register again (without generating any ADEINT interrupt request) and then the ADC is ...
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Known limitations Figure 38. ADC injection actual operation 126/185 ST10F271Z1 ADEINT Interrupt not generated ADDAT2 correctly updated and can be read by software ...
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ST10F271Z1 24.2 Concurrent transmission requests in DAR-mode (C-CAN module) Description When the C-CAN module is configured to operate in DAR-mode (Disable Automatic Retransmission) and the host requests the transmission of several messages at the same time, only two of these ...
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Known limitations 24.3 Transmission request disabled (C-CAN module) Description The transmission request of a message object may remain disabled (even if the host immediately enables it again) in the following situations the host disables the pending transmission request ...
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ST10F271Z1 24.4 Spurious BREQ pulse in slave mode during external bus arbitration phase Description Sporadic bus errors may occur when external bus arbitration is used via the HOLD function and the ST10F272Z2 is configured as a slave. After the slave ...
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Known limitations 24.5 Flash wake-up from idle mode Description When waking up from idle mode, the Flash response time is slower than in running mode. This can lead to an incorrect data read or code fetch when the CPU frequency ...
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ST10F271Z1 multiplexed bus with memory tristate wait state is used, the PWRDN instruction must be executed from internal RAM or XRAM. 24.7 Flash wake-up from power-down mode Description When waking up from interruptible power-down mode, the Flash response time is ...
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Known limitations 3) Load the Tx timer with the CCy register minus 1: MOV TxREL, #value MOV Tx, #( value-1) bfldl/bfldh TxxCON , #mask, #data or MOV TxxCON, #data 132/185 ST10F271Z1 ...
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ST10F271Z1 25 Electrical characteristics 25.1 Absolute maximum ratings Table 60. Absolute maximum ratings Symbol V Voltage on V pins with respect to ground ( Voltage on V pin with respect to ground (V STBY STBY V Voltage ...
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Electrical characteristics 25.2 Recommended operating conditions Table 61. Recommended operating conditions Symbol V Operating supply voltage DD V Operationg stand-by supply voltage STBY V Operating analog reference voltage AREF T Ambient temperature under bias A T Junction temperature under bias ...
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ST10F271Z1 Table 62. Thermal characteristics Symbol Thermal Resistance Junction-Ambient PQFP 144 - 3 0.65 mm pitch Θ LQFP 144 - 0.5 mm pitch JA LQFP 144 - 20 x ...
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Electrical characteristics Table 64. DC characteristics (continued) Parameter Input low voltage READY (TTL only) Input high voltage (TTL mode) (except RSTIN, EA, NMI, RPD, XTAL1) Input high voltage (CMOS mode) (except RSTIN, EA, NMI, RPD, XTAL1) Input high voltage RSTIN, ...
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ST10F271Z1 Table 64. DC characteristics (continued) Parameter (4) Input leakage current (P2[0]) Input leakage current (RPD) Input leakage current ( P3[12], P3[15]) Overload current (all except P2[0]) (4) Overload current (P2[0]) RSTIN pull-up resistor (6) (7) Read/Write inactive current (6) ...
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Electrical characteristics Table 64. DC characteristics (continued) Parameter (12) Stand-by supply current (RTC on, 32 kHz Oscillator on, main V off, V on) DD STBY (1) (12) Stand-by supply current (V transient condition Not 100% tested, guaranteed by ...
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ST10F271Z1 Figure 40. Port2 test mode structure Fast external interrupt input Figure 41. Supply current versus the operating frequency (run and idle modes) 150 100 Clock Input Alternate data input latch Test mode Flash sense amplifier and ...
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Electrical characteristics 25.6 Flash characteristics = 5 V ± 10 Table 65. Flash characteristics Parameter (2) Word program (32-bit) (2)) Double word program (64-bit) Bank 0 program (128K) (double word program) Sector erase (8K) Sector erase (32K) ...
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... Total unadjusted error Coupling factor between inputs Input pin capacitance 3) 8) Sampling capacitance (average ambient temperature 60°C) 128 Kbyte (code store) > 20 years - - - ST10F2xx”). Contact your local field service, local sales person or STMicroelectronics = –40 to +125 °C, 4.5 V ≤ 0 Limit values Symbol min ...
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Electrical characteristics Table 67. A/D converter characteristics Parameter 3) 8) Analog switch resistance 1. V can be tied to ground when A/D Converter is not in use: an extra consumption (around 200 AREF main V is added due to internal ...
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ST10F271Z1 Fast conversion can be achieved by programming the respective times to their absolute possible minimum. This is preferable for scanning high frequency signals. The internal resistance of analog source and analog supply must be sufficiently low, however. High internal ...
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Electrical characteristics These four error quantities are explained below using characteristic. Offset error Offset error is the deviation between actual and ideal A/D conversion characteristics when the digital output value changes from the minimum (zero voltage OFS). ...
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ST10F271Z1 Figure 42. A/D conversion characteristic 3FF 3FE 3FD 3FC 3FB 3FA Digital Out 007 (HEX) 006 005 004 003 002 001 000 1 Offset Error OFS 25.7.4 Analog reference pins The accuracy of the A/D converter depends on how ...
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Electrical characteristics besides, it sources charge during the sampling phase, when the analog signal source is a high-impedance source. A real filter, can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC ...
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ST10F271Z1 The formula above provides a constraints for external network design, in particular on resistive path. A second aspect involving the capacitance network shall be considered. Assuming the three capacitances equivalent circuit reported in Figure 40), ...
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Electrical characteristics R sizing is obtained course, R combination with R definitively bigger than C charge transfer transient) will be much higher than V respected (charge balance assuming now C The two transients above are not influenced by ...
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ST10F271Z1 From this formula, in the worst case (when V assuming to accept a maximum error of half a count (~2.44 mV immediately evident a constraints the next section an example of how to ...
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Electrical characteristics 1. Supposing to design the filter with the pole exactly at the maximum frequency of the signal, the time constant of the filter is: 2. Using the relation between possible to define ...
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ST10F271Z1 25.8 AC characteristics 25.8.1 Test waveforms Figure 46. Input / output waveforms 2.4V 0.4V AC inputs during testing are driven at 2.4 V for a logic ‘1’ and 0.4 V for a logic ‘0’. Timing measurements are made at ...
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Electrical characteristics Figure 48. Generation mechanisms for the CPU clock Phase Locked Loop operation f XTAL f CPU Direct clock drive f XTAL f CPU Prescaler operation f XTAL f CPU 25.8.3 Clock generation modes Next Table 69 associates the ...
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ST10F271Z1 25.8.4 Prescaler operation When pins P0.15-13 (P0H.7-5) equal ’001’ during reset, the CPU clock is derived from the internal oscillator (input clock signal 2:1 prescaler. The frequency of f the duration of an individual TCL) is defined ...
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Electrical characteristics an external clock failure occurs, then the watchdog counter overflows (after 16 PLL clock cycles). The CPU clock signal will be switched to the PLL free-running clock signal, and the oscillator watchdog Interrupt Request is flagged. The CPU ...
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ST10F271Z1 Table 70. Internal PLL divider mechanism (continued) P0.15-13 XTAL frequency (P0H.7- 6.4MHz 8MHz 4MHz The PLL input frequency range is limited 3.5 ...
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Electrical characteristics Jitter in the input clock PLL acts like a low pass filter for any jitter in the input clock. Input clock jitter with the frequencies within the PLL loop bandwidth is passed to the PLL output and higher ...
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ST10F271Z1 Figure 49. ST10F271Z1 PLL jitter ±5 ±4 ±3 ±2 ±1 T JIT 0 0 25.8.10 PLL lock / unlock During normal operation, if the PLL gets unlocked for any reason, an interrupt request to the CPU is generated, and ...
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Electrical characteristics Table 71. PLL characteristics (V Symbol T PLL Start-up time PSUP T PLL Lock-in time LOCK Single Period Jitter T JIT (cycle to cycle = 2 TCL) F PLL free running frequency free 1. Not 100% tested, guaranteed ...
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ST10F271Z1 Table 73. Main oscillator negative resistance (module) C min. 545 Ω 4 MHz 240 Ω 8 MHz The given values of C printed circuit board: the negative resistance values are calculated assuming additional 5pF to the values in the ...
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Electrical characteristics Table 75. Minimum values of negative resistance (module) for 32 kHz oscillator kHz - The given values of C printed circuit board: the negative resistance values are calculated assuming additional 5pF ...
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ST10F271Z1 Figure 52. External clock drive XTAL1 Note: When Direct Drive is selected, an external clock source can be used to drive XTAL1. The maximum frequency of the external clock source depends on the duty cycle: when 64MHz is used, ...
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Electrical characteristics Table 78. Multiplexed bus timings Symbol Parameter t CC ALE high time Address setup to ALE Address hold after ALE 7 ALE falling edge to RD (with RW-delay) ...
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ST10F271Z1 Table 78. Multiplexed bus timings (continued) Symbol Parameter ALE fall. edge to RdCS, WrCS (no RW delay) Address float after RdCS WrCS (with RW delay)1 Address float after RdCS WrCS ...
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Electrical characteristics Figure 53. External memory cycle: multiplexed bus, with/without read/write delay, normal ALE ALE t 6 CSx A23-A16 (A15-A8) BHE Read cycle Address/data bus (P0) RD Write cycle Address/data bus (P0) WR WRL WRH 164/185 ...
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ST10F271Z1 Figure 54. External memory cycle: multiplexed bus, with/without read/write delay, extended ALE t 5 ALE t 6 CSx t 6 A23-A16 (A15-A8) BHE Read cycle t 6 Address/data bus (P0) RD Write cycle Address/Data Bus (P0) WR WRL WRH ...
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Electrical characteristics Figure 55. External memory cycle: multiplexed bus, with/without r/w delay, normal ALE, r/w CS CLKOUT ALE A23-A16 (A15-A8) BHE Read cycle Address/data bus (P0) RdCSx Write cycle Address/data Bus (P0) WrCSx 166/185 ...
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ST10F271Z1 Figure 56. External memory cycle: multiplexed bus, with/without r/w delay, extended ALE, r/w CS CLKOUT t ALE t 6 A23-A16 (A15-A8) BHE Read cycle t 6 Address/data bus (P0) RdCSx Write cycle Address/data bus (P0) WrCSx ...
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Electrical characteristics 25.8.17 Demultiplexed bus ± 10 ALE cycle time = 4 TCL + 2t Table 79. Demultiplexed bus timings Symbol Parameter t CC ALE high time Address setup to ALE ...
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ST10F271Z1 Table 79. Demultiplexed bus timings (continued) Symbol Parameter ALE falling edge to latched Latched CS low to valid data Latched CS hold after RD Address setup to ...
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Electrical characteristics Figure 57. External memory cycle: demultiplexed bus, with/without r/w delay, normal ALE CLKOUT ALE CSx A23-A16 A15-A0 (P1) BHE Read cycle Data bus (P0) (D15-D8) D7-D0 RD Write cycle Data bus (P0) (D15-D8) D7-D0 WR WRL WRH 170/185 ...
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ST10F271Z1 Figure 58. Exteral memory cycle: demultiplexed bus, with/without r/w delay, extended ALE CLKOUT ALE t CSx A23-A16 A15-A0 (P1) BHE Read cycle Data bus (P0) (D15-D8) D7-D0 RD Write cycle Data bus (P0) (D15-D8) D7-D0 WR WRL WRH t ...
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Electrical characteristics Figure 59. External memory cycle: demultiplexed bus, with/without r/w delay, normal ALE, r/w CS CLKOUT ALE A23-A16 A15-A0 (P1) BHE Read cycle Data bus (P0) (D15-D8) D7-D0 RdCSx Write cycle Data bus (P0) (D15-D8) D7-D0 WrCSx 172/185 t ...
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ST10F271Z1 Figure 60. External memory cycle: demultiplexed bus, without r/w delay, extended ALE, r/w CS CLKOUT ALE A23-A16 A15-A0 (P1) BHE Read cycle Data bus (P0) (D15-D8) D7-D0 RdCSx Write cycle Data bus (P0) (D15-D8) D7-D0 WrCSx ...
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Electrical characteristics 25.8.18 CLKOUT and READY ± 10 Table 80. CLKOUT and READY timings Symbol Parameter t CC CLKOUT cycle time CLKOUT high time CLKOUT low time 31 ...
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ST10F271Z1 Figure 61. CLKOUT and READY CLKOUT ALE RD, WR Synchronous READY Asynchronous READY 1. Cycle as programmed, including MCTC wait states (Example shows 0 MCTC WS). 2. The leading edge of the respective command depends on RW-delay. 3. READY ...
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Electrical characteristics 25.8.19 External bus arbitration = 5 V ± Table 81. External bus arbitration timings Symbol HOLD input setup time CLKOUT CLKOUT to HLDA high BREQ ...
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ST10F271Z1 Figure 63. External bus arbitration (regaining the bus) CLKOUT HOLD HLDA BREQ CSx (On P6.x) Other signals 1. This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is ...
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Electrical characteristics 25.8.20 High-speed synchronous serial interface (SSC) timing Master mode ±10 Table 82. SSC master mode timings Symbol Parameter t CC SSC clock cycle time 300 t CC SSC clock high time 301 ...
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ST10F271Z1 Figure 64. SSC master timing 1) SCLK MTSR MRST 1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock edge as shift edge (drawn in bold), with latch on ...
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Electrical characteristics Table 83. SSC slave mode timings (continued) Symbol Parameter Read data setup time before latch SR edge, phase error detection off t 317 (SSCPEN = 0) Read data hold time after latch SR edge, phase error detection off ...
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ST10F271Z1 26 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner ...
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Package information Figure 66. PQFP144 - 144-pin plastic quad flatpack mm, 0.65 mm pitch, package outline 109 144 Table 84. PQFP144 - 144-pin plastic quad flatpack mm, 0.65 mm pitch, package mechanical data Symbol ...
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ST10F271Z1 Figure 67. LQFP144 - 144 pin low profile quad flat package 20x20 mm, 0.5 mm pitch, package outline 108 109 b 144 1 Table 85. LQFP144 - 144 pin low profile quad flat package 20x20mm, 0.5 mm pitch, package ...
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Revision history 27 Revision history Table 86. Document revision history Date 30-Jun-2006 18-Jan-2008 184/185 Revision 1 Initial release. ST10F271 replaced by ST10F271Z1 Added Section 24: Known limitations on page 123 Modified example page 154 Section 26: ...
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... ST10F271Z1 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...