ZGP323HEH4832C00TR Zilog, ZGP323HEH4832C00TR Datasheet - Page 54
ZGP323HEH4832C00TR
Manufacturer Part Number
ZGP323HEH4832C00TR
Description
IC Z8 GP MCU 32K OTP 48SSOP
Manufacturer
Zilog
Series
Z8® GP™r
Specifications of ZGP323HEH4832C00TR
Core Processor
Z8
Core Size
8-Bit
Speed
8MHz
Peripherals
HLVD, POR, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Ram Size
237 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
48-SSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
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PS023807-0707
Port Configuration Register
The Port Configuration (PCON) register
Port 3. It is located in the expanded register 2 at Bank F, location 00.
Comparator Output Port 3 (D0)
Bit 0 controls the comparator used in Port 3. A 1 in this location brings the comparator
outputs to P34 and P37, and a 0 releases the Port to its standard I/O configuration.
Port 1 Output Mode (D1)
Bit 1 controls the output mode of port 1. A 1 in this location sets the output to push-pull,
and a 0 sets the output to open-drain.
Port 0 Output Mode (D2)
Bit 2 controls the output mode of port 0. A 1 in this location sets the output to push-pull,
and a 0 sets the output to open-drain.
Stop Mode Recovery Register (SMR)
This register selects the clock divide value and determines the mode of Stop Mode Recov-
ery
that is hardware set on the condition of Stop recovery and reset by a power-on cycle. Bit 6
D7
* Default setting after reset.
PCON(FH)00H
(Figure
Figure 30. Port Configuration Register (PCON) (Write Only)
D6
D5
31). All bits are write only except bit 7, which is read only. Bit 7 is a flag bit
D4
D3
D2
D1
D0
(Figure
30) configures the comparator output on
Comparator Output Port 3
0 P34, P37 Standard Output*
1 P34, P37 Comparator Output
Port 1
0: Open-Drain
1: Push-Pull*
Port 0
0: Open-Drain
1: Push-Pull*
Reserved (Must be 1)
Product Specification
Functional Description
ZGP323H
49
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